Parallel-to-serial interface circuit and transmission device having the same

A parallel-to-serial interface circuit, comprising:

• a parallel-to-serial converter configured to convert parallel data in series in response to a first clock signal to generate odd data and even data;
• an equalizer configured to shift the odd data in response to a second clock signal to delay the odd data by a half period of the second clock signal and sequentially generate odd pre data, odd main data, and odd post data, and shift the even data in response to the second clock signal to delay the even data by a half period of the second clock signal and sequentially generate even pre data, even main data, and even post data;
• an equalizer selection unit configured to, in response to an equalizer enable signal, select and output the even pre data and the odd pre data, select and output inverted odd main data obtained by inverting the odd main data and inverted even main data obtained by inverting the even main data, and select and output the even post data and the odd post data;
• a differential data generator configured to, in response to a third clock signal, generate a differential even pre data pair including the even pre data and inverted even pre data obtained by inverting the even pre data, generate a differential odd main data pair including the inverted odd main data and odd main data obtained by inverting the inverted odd main data, and generate a differential even post data pair including the even post data and inverted even post data obtained by inverting the even post data, or generate a differential odd pre data pair including the odd pre data and inverted odd pre data obtained by inverting the odd pre data, generate a differential even main data pair including the inverted even main data and even main data obtained by inverting the inverted even main data, and generate a differential odd post data pair including the odd post data and inverted odd post data obtained by inverting the odd post data;
• a final parallel-to-serial converter configured to, in response to a fourth clock signal, sequentially and alternately select the differential even pre data pair and the differential odd pre data pair to generate a differential pre data pair, sequentially and alternately select the inverted differential odd main data pair and the inverted differential even main data pair to generate an inverted differential main data pair, and sequentially and alternately select the differential even post data pair and the differential odd post data pair to generate a differential post data pair;
• and
• a driver configured to drive the differential even pre data pair based on a pre-cursor coefficient to generate a differential pre data level pair, drive the inverted differential main data pair based on a main-cursor coefficient to generate an inverted differential main data level pair, and drive the differential post data pair based on a post-cursor coefficient to generate a differential post data level pair, wherein:
• the first clock signal and the fourth clock signal are generated by being supplied with a first internal power supply voltage and a second internal power supply voltage separated from each other,
• the odd pre data is generated at the same time as the even main data, and
• the differential pre data level pair, the inverted differential main data level pair, and the differential post data level pair are summed at an output node pair of the driver.

A transmission device, comprising:

• a parallel-to-serial interface circuit configured to convert internally generated parallel data in series to output data, wherein:
• the parallel-to-serial interface circuit includes:
• a parallel-to-serial converter configured to convert the parallel data in series in response to a first clock signal to generate odd data and even data;
• an equalizer configured to shift the odd data in response to a second clock signal to delay the odd data by a half period of the second clock signal and sequentially generate odd pre data, odd main data, and odd post data, and shift the even data in response to the second clock signal to delay the even data by a half period of the second clock signal and sequentially generate even pre data, even main data, and even post data;
• a final parallel-to-serial converter configured to, in response to a third clock signal, sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data obtained by inverting the odd main data and inverted even main data obtained by inverting the even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data;
• and
• a driver configured to drive the pre data based on a pre-cursor coefficient to generate a pre data level, drive the inverted main data based on a main-cursor coefficient to generate an inverted main data level, and drive the post data based on a post-cursor coefficient to generate a post data level,
• the first clock signal and the third clock signal are generated by being supplied with a first internal power supply voltage and a second internal power supply voltage separated from each other,
• the odd pre data is generated at the same time as the even main data, and
• the pre data level, the inverted main data level, and the post data level are summed at an output node of the driver.