Reference bits test and repair using memory built-in self-test
AssigneeSiemens Industry Software Inc.
InventorsJongsin Yun, Benoit Nadeau-Dostie, Harshitha Kodali
Life of this patent
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Abstract
A memory-testing circuit configured to perform a test of reference bits in a memory. In a read operation, outputs of data bit columns are compared with one or more reference bit columns. The memory-testing circuit comprises: a test controller and association adjustment circuitry configurable by the test controller to associate another one or more reference bit columns or one or more data bit columns with the data bit columns in the read operation. The test controller can determine whether the original one or more reference bit columns have a defect based on results from the two different association.
Claims14
A memory-testing circuit in a circuit configured to perform a test of a memory in the circuit, the memory comprising:
- data bit columns configured to store data bits, reference bit columns configured to store reference bits, and column association circuitry configured to associate one or more of the reference bit columns with a data bit column in the data bit columns, the memory-testing circuit comprising:
- a test controller, and
- association adjustment circuitry coupled to the column association circuitry and the test controller, the association adjustment circuitry configurable by the test controller to associate another one or more of the reference bit columns or one or more of the data bit columns with the data bit column in the data bit columns,
- wherein the test of the memory comprises:
- performing one or more read operations based on one or more of the reference bit columns associated by the column association circuitry to generate one or more outputs,
- comparing the one or more outputs with corresponding good-machine values to determine whether any of the one or more outputs is incorrect,
- if at least one of the one or more outputs is incorrect, repeating at least one of the one or more read operations that generates the at least one of the one or more outputs based on another one or more of the reference bit columns or one or more of the data bit columns which are associated by the association adjustment circuitry to generate at least one second output, and
- comparing the at least one second output with the corresponding good machine value to determine whether the one or more of the reference bit columns associated by the column association circuitry have a defect.
One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:
- creating a memory-testing circuit in a circuit design, the circuit design comprising a memory, the memory-testing circuit configured to perform a test of the memory, the memory comprising:
- data bit columns configured to store data bits, reference bit columns configured to store reference bits, and column association circuitry configured to associate one or more of the reference bit columns with a data bit column in the data bit columns, the memory-testing circuit comprising:
- a test controller, and
- association adjustment circuitry coupled to the column association circuitry and the test controller, the association adjustment circuitry configurable by the test controller to associate another one or more of the reference bit columns or one or more of the data bit columns with the data bit column in the data bit columns,
- wherein the test of the memory comprises:
- performing one or more read operations based on one or more of the reference bit columns associated by the column association circuitry to generate one or more outputs,
- comparing the one or more outputs with corresponding good-machine values to determine whether any of the one or more outputs is incorrect,
- if at least one of the one or more outputs is incorrect, repeating at least one of the one or more read operations that generates the at least one of the one or more outputs based on another one or more of the reference bit columns or one or more of the data bit columns which are associated by the association adjustment circuitry to generate at least one second output, and
- comparing the at least one second output with the corresponding good machine value to determine whether the one or more of the reference bit columns associated by the column association circuitry have a defect.
Dependencies are inferred from the claim text.