Nonvolatile semiconductor memory device
AssigneeKioxia Corporation
InventorTakashi MAEDA
Life of this patent
Estimating the term…
Abstract
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.
Claims21
(canceled)
A method for controlling a memory device, comprising:
- performing a first erase operation of erasing data stored in a plurality of first memory cells in a first sub memory block, while erasing data stored in a plurality of second memory cells in a second sub memory block being prohibited,
- wherein the memory device including
- a memory cell array including a memory block, the memory block including the first sub memory block and the second sub memory block, the first sub memory block including the plurality of first memory cells, and the second sub memory block including the plurality of second memory cells;
- a first drain side selective transistor electrically connected to the first memory cells;
- a second drain side selective transistor electrically connected to the second memory cells;
- a first source side selective transistor electrically connected to the first memory cells;
- a second source side selective transistor electrically connected to the second memory cells;
- a source line electrically connected to the first source side selective transistor and the second source side selective transistor;
- a plurality of first word lines electrically connected to gates of the first memory cells;
- and
- a plurality of second word lines electrically connected to gates of the second memory cells.
Dependencies are inferred from the claim text.