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AssigneeSamsung Electronics Co., Ltd.
InventorsSung-Rae KIM, Kijun LEE, Myungkyu LEE, Sunghye CHO, Jin-Hoon JANG, Isak HWANG
Estimating the term…
Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.
A memory device, comprising:
An error correction code (ECC) circuit configured to correct first data based on the first data and first parity data stored in a memory device, comprising:
An operation method of an error correction code (ECC) circuit configured to correct first data based on the first data and first parity data stored in a memory device, the method comprising:
(canceled)
Dependencies are inferred from the claim text.