Systems and methods for accelerating the computation of the reciprocal function and the reciprocal-square-root function

Computer storage media storing a configuration file, the configuration file specifying a configuration of a field programmable gate array (FPGA) comprising a configurable interconnect fabric and a plurality of logic blocks, where an FPGA configured based on the configuration file comprises logic blocks, connected by the configurable interconnect fabric, implementing:

• a mantissa computation stage comprising a mantissa portion of a reciprocal function data path, implemented by the logic blocks and the configurable interconnect fabric, configured to:
• partition an M-bit mantissa component of an input floating-point value into L most-significant bits and M-L least significant bits;
• lookup a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table comprising a reciprocal lookup table;
• and
• compute an output mantissa component of an output floating-point value by multiplying the slope value by the M-L least significant bits to compute a product and adding the offset value to the product;
• and
• an exponent computation stage comprising a plurality of adders, implemented by the logic blocks and the configurable interconnect fabric, configured to compute an output exponent component of the output floating-point value, the computing the output exponent component comprising negating an exponent component of the input floating-point value.

A method for accelerating computations in a field programmable gate array (FPGA) comprising a configurable interconnect fabric connecting a plurality of logic blocks, the method comprising:

• partitioning, by a mantissa computation stage of the FPGA implemented by the configurable interconnect fabric and the plurality of logic blocks, an M-bit mantissa component of an input floating-point value into L most-significant bits and M-L least significant bits;
• looking up, by the mantissa computation stage, a slope value and an offset value, based on the L most significant bits, from a linear interpolation lookup table comprising a reciprocal lookup table;
• computing, by the mantissa computation stage, an output mantissa component of an output floating-point value by multiplying, by an integer adder of the mantissa computation stage, the slope value by the M-L least significant bits to compute a product and adding the offset value to the product;
• and
• computing, by an exponent computation stage implemented by the configurable interconnect fabric and the plurality of logic blocks, an output exponent component of the output floating-point value, the computing the output exponent component comprising negating an exponent component of the input floating-point value.