Display Apparatus

A display apparatus comprising:

• a substrate comprising a display area and a non-display area that is adjacent to the display area;
• a first thin film transistor in the display area, the first thin film transistor comprising a first semiconductor pattern comprising a first oxide semiconductor, a first gate electrode overlapping the first semiconductor pattern, a first source electrode connected to the first semiconductor pattern, and a first drain electrode connected to the first semiconductor pattern;
• a second thin film transistor in the display area, the second thin film transistor comprising a second semiconductor pattern comprising a second oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern;
• a third thin film transistor in the non-display area, the third thin film transistor comprising a third semiconductor pattern comprising a third oxide semiconductor, a third gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern;
• a first conductive pattern under the first semiconductor pattern and overlapping with the first semiconductor pattern;
• a second conductive pattern under the second semiconductor pattern and overlapping with the second semiconductor pattern;
• and
• a third semiconductor pattern under the third semiconductor pattern and overlapping with the third semiconductor pattern;
• wherein a first thickness of an insulating layer between the first semiconductor pattern and the first conductive pattern is less than a second thickness of an insulating layer between the second semiconductor pattern and the second conductive pattern.

A display apparatus comprising:

• a substrate comprising a display area and a non-display area that is adjacent to the display area;
• a first thin film transistor in the display area of the substrate, the first thin film transistor comprising a first semiconductor pattern comprising a first oxide semiconductor, a first gate electrode overlapping the first semiconductor pattern such that a second gate insulating layer is interposed between the first gate electrode and the first semiconductor pattern, a first source electrode connected to the first semiconductor pattern, and a first drain electrode connected to the first semiconductor pattern;
• a second thin film transistor in the display area of the substrate, the second thin film transistor comprising a second semiconductor pattern comprising a second oxide semiconductor, a second gate electrode overlapping the second semiconductor pattern, a second source electrode connected to the second semiconductor pattern, and a second drain electrode connected to the second semiconductor pattern;
• a third thin film transistor in the non-display area of the substrate, the third thin film transistor comprising a third semiconductor pattern comprising a first polysilicon on a first buffer layer, a third gate electrode overlapping the third semiconductor pattern such that a first gate insulating layer is interposed between the third gate electrode and the third semiconductor pattern, a third source electrode connected to the third semiconductor pattern, and a third drain electrode connected to the third semiconductor pattern;
• a first conductive pattern between the display area of the substrate and the first semiconductor pattern of the first thin film transistor;
• a second conductive pattern between the display area of the substrate and the second semiconductor pattern of the second thin film transistor;
• and
• a second buffer layer including a silicon nitride layer interposed between the first semiconductor pattern and the first conductive pattern,
• wherein a first thickness of an insulating layer between the first semiconductor pattern and the first conductive pattern is less than a second thickness of an insulating layer between the second semiconductor pattern and the second conductive pattern.