Semiconductor memory devices

A semiconductor memory device comprising:

• a substrate including an active pattern;
• a bit line crossing the active pattern;
• a storage node contact adjacent to the bit line;
• a spacer structure that is between the bit line and the storage node contact;
• a first trench and a second trench on the spacer structure, the second trench being between the first trench and the spacer structure;
• a landing pad electrically connected to the storage node contact;
• an insulating pattern in the first trench and the second trench;
• a liner enclosing the insulating pattern,
• wherein the liner comprises:
• an upper liner in the first trench;
• and
• a lower liner in the second trench,
• wherein the largest thickness of the upper liner is larger than the largest thickness of the lower liner.

A semiconductor memory device comprising:

• a substrate including an active pattern comprising a first source/drain region and a pair of second source/drain regions, wherein the second source/drain regions are spaced apart from each other and have the first source/drain region therebetween;
• a device isolation layer on the substrate in a trench defining the active pattern;
• a word line extending in a first direction across the active pattern;
• a gate dielectric layer between the word line and the active pattern;
• a word line capping pattern on the word line;
• an interlayer insulating pattern on the word line capping pattern;
• a bit line that is electrically connected to the first source/drain region, is on the interlayer insulating pattern, and extends in a second direction crossing the first direction, the bit line comprising a bit line polysilicon pattern, a bit line diffusion prevention pattern, and a bit line metal pattern that are sequentially stacked;
• a spacer structure on a side surface of the bit line;
• a storage node contact that is coupled to one of the second source/drain regions and is spaced apart from the bit line by the spacer structure;
• a landing pad electrically connected to the storage node contact;
• an insulating pattern on the spacer structure and adjacent to the landing pad;
• a liner between the insulating pattern and the landing pad;
• and
• a data storage pattern on the landing pad,
• wherein the insulating pattern comprises:
• an upper insulating portion;
• and
• a lower insulating portion between the upper insulating portion and the spacer structure,
• wherein the largest width of the lower insulating portion is larger than the smallest width of the upper insulating portion.