Trench-type beol memory cell

An integrated chip, comprising:

• a substrate;
• a metal interconnect over the substrate, the metal interconnect comprising a metallization layer;
• a dielectric structure over the metallization layer;
• three or more openings that extend through the dielectric structure;
• a memory cell comprising a lower electrode, a data storage layer, and an upper electrode disposed over and the dielectric structure and within each of the three or more openings;
• wherein each of the lower electrode, the data storage layer, and the upper electrode descend into the three or more openings and over the dielectric structure lateral to the three or more openings;
• and
• the three or more openings are disposed in a two-dimensional arrangement.

A method comprising:

• forming a lower interconnect within a lower dielectric structure over a substrate;
• forming an etch stop layer over the lower dielectric structure;
• forming an inter-level dielectric layer over the etch stop layer;
• etching a plurality of openings through the inter-level dielectric layer;
• forming a memory cell stack over the inter-level dielectric layer and in the openings;
• etching to define a memory cell from the memory cell stack;
• wherein an upper electrode of the memory cell descends into each of the openings;
• and
• a portion of the memory cell extends laterally from the openings over the inter-level dielectric layer.