Erasable programmable single-ploy non-volatile memory cell and associated array structure
AssigneeeMemory Technology Inc.
InventorHsueh-Wei CHEN
Life of this patent
Estimating the term…
Abstract
An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
Claims20
An array structure of erasable programmable non-volatile memory cells, the array structure being constructed in a semiconductor substrate, the array structure comprising:
- an isolation structure formed on the semiconductor substrate, wherein a surface of the semiconductor substrate is divided into a first region and a second region by the isolation structure;
- a well region formed in the surface of the semiconductor substrate corresponding to the first region;
- a first gate structure and a second gate structure formed on the surface of the semiconductor substrate corresponding to the first region, wherein the first region is divided into a first sub-region, a second sub-region and a third sub-region by the first gate structure and the second gate structure, wherein the first sub-region is located beside a first side of the first gate structure, the second sub-region is arranged between a second side of the first gate structure and a first side of the second gate structure, and the third sub-region is located beside a second side of the second gate structure, wherein the first gate structure is connected to a first select gate line, an extension segment of the second gate structure is externally extended from the second gate structure through a surface of the isolation structure, a portion of the second region is covered by a first portion of the second gate structure, and a portion of the third sub-region is covered by a second portion of the second gate structure;
- a first doped region, a second doped region and a third doped region formed in the surface of the semiconductor substrate corresponding to the first sub-region, the second sub-region and the third sub-region, respectively, wherein the first doped region is connected to a first source line, and the third doped region is connected to a first bit line;
- and
- a fourth doped region formed in the surface of the semiconductor substrate corresponding to the second region, wherein the fourth doped region is connected to an erase line;
- wherein the first doped region, the first gate structure and the second doped region are collaboratively formed as a first select transistor, the second doped region, the second gate structure and the third doped region are collaboratively formed as a first floating gate transistor, the first portion of the second gate structure and the fourth doped region are collaboratively formed as a first capacitor, and the second portion of the second gate structure and the third doped region are collaboratively formed as a second capacitor, wherein a first memory cell of the array structure comprises the first select transistor, the first floating gate transistor, the first capacitor and the second capacitor.
Dependencies are inferred from the claim text.