US 2023/0157016 A1 · SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Abstract

A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Claims20

Dependent claims

A semiconductor device, comprising:

a peripheral circuit region comprising a plurality of complementary metal-oxide-semiconductor components;
a substrate on the peripheral circuit region comprising:
an N-type doped poly silicon layer on the peripheral circuit region;
an oxide layer on the N-type doped poly silicon layer;
and
a conductive layer on the oxide layer;
and
to an array region on the substrate comprising:
a plurality of gate structures and a plurality of insulating layers alternately stacked on the conductive layer, wherein a bottommost gate structure of the gate structures and the conductive layer together serve as a plurality ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4;
and
a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

8 more elements

A method of fabricating a semiconductor device, comprising:

providing a structure, the structure comprising:
a peripheral circuit region comprising a plurality of complementary metal-oxide-semiconductor components;
a substrate on the peripheral circuit region comprising:
a first poly silicon layer on the peripheral circuit region,
wherein the first poly silicon layer is doped with N-type dopants;
a first oxide layer on the first poly silicon layer;
a second poly silicon layer on the first oxide layer;
a second oxide layer on the second poly silicon layer;
a third poly silicon layer on the second oxide layer;
a third oxide layer on the third poly silicon layer;
and
a fourth poly silicon layer on the third oxide layer;
and
an array region on the substrate comprising:
a plurality of first insulating layers and a plurality of second insulating layers alternately stacked on the fourth poly silicon layer;
and
a vertical channel structure penetrating the first insulating layers and the second insulating layers and extending into the first poly silicon layer;
to removing the fourth poly silicon layer thereby forming a first cavity between the third oxide layer and a bottommost first insulating layer of the first insulating layers;
and
filling the first cavity with a conductive line.

17 more elements

Dependencies are inferred from the claim text.

Semiconductor device and method of fabricating the same

Life of this patent

Semiconductor device and method of fabricating the same

Life of this patent

Abstract

Claims20