Anti-fuse device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMin-Shin WU, Meng-Sheng CHANG, Shao-Yu CHOU, Yao-Jen YANG
Life of this patent
Estimating the term…
Abstract
An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.
Claims20
An integrated circuit (IC) device comprising:
- an active area positioned in a substrate;
- first and second contact structures overlying and electrically connected to the active area;
- a conductive element overlying and electrically connected to each of the first and second contact structures;
- an anti-fuse transistor device comprising a dielectric layer between a gate structure and the active area;
- a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure;
- and
- a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.
An integrated circuit (IC) device comprising:
- an active area positioned in a substrate;
- first through third contact structures overlying and electrically connected to the active area;
- a conductive element overlying and electrically connected to each of the first through third contact structures;
- first and second anti-fuse transistor devices, each comprising a dielectric layer between a corresponding gate structure and the active area;
- a first selection transistor overlying the active area adjacent to each of the first anti-fuse transistor device and the first contact structure;
- a second selection transistor overlying the active area adjacent to each of the first anti-fuse transistor device and the second contact structure;
- a third selection transistor overlying the active area adjacent to each of the second anti-fuse transistor device and the second contact structure;
- and
- a fourth selection transistor overlying the active area adjacent to each of the second anti-fuse transistor device and the third contact structure.
A method of operating a circuit, the method comprising:
- receiving a voltage at a gate of an anti-fuse transistor device overlying an active area positioned in a substrate;
- receiving a signal at each of
- a gate of a first selection transistor positioned between the anti-fuse transistor and a first contact structure coupled between the active area and a bit line, and
- a gate of a second selection transistor coupled between the anti-fuse transistor device and a second contact structure coupled between the active area and the bit line;
- and
- in response to the signal having a first voltage value, switching on each of the first and second selection transistors.
Dependencies are inferred from the claim text.