Semiconductor memory device and method of fabricating the same

A semiconductor memory device, comprising:

• a stack structure including layer groups that are vertically stacked on a substrate, the layer groups each including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer;
• and
• a bit line on one side of the stack structure, the bit line extending vertically, wherein:
• the word line of each of the layer groups extends horizontally,
• the layer groups include a first layer group, a second layer group, and a third layer group that are sequentially stacked, and
• a first vertical interval between the channel layer of the first layer group and the channel layer of the second layer group is different from a second vertical interval between the channel layer of the second layer group and the channel layer of the third layer group.

A semiconductor memory device, comprising:

• a stack structure including layer groups that are vertically stacked on a substrate, the layer groups each including a memory cell transistor and a data storage element electrically connected to the memory cell transistor;
• and
• a bit line on one side of the stack structure, the bit line extending vertically, wherein:
• the bit line electrically connects the memory cell transistors of the layer groups, the memory cell transistors being stacked,
• the memory cell transistor of each layer group includes:
• a channel layer between the bit line and the data storage element;
• and
• a word line adjacent to the channel layer,
• the layer groups include a first layer group, a second layer group, and a third layer group that are sequentially stacked,
• a structure of the memory cell transistor of the first layer group and a structure of the memory cell transistors of the second layer group are mirror-symmetrical to each other about a central line between the first layer group and the second layer group, and
• a structure of the memory cell transistor of the third layer group is the same as the structure of the memory cell transistor of the first layer group.