Track-And-Hold Circuit

A track-and-hold circuit, comprising:

• 2N bias adjusting circuits configured to adjust a DC bias voltage of input differential clock signals including a positive-phase clock signal and a negative-phase clock signal, wherein N is an integer equal to or more than 2;
• and
• 2N sampling circuits each including a signal input terminal, a signal output terminal, a positive-phase clock input terminal, and a negative-phase clock input terminal second clock input terminal, the 2N sampling circuits each being configured to switch between:
• a track mode in which an output signal output from the signal output terminal tracks an input signal input to the signal input terminal;
• and
• a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with the positive-phase clock signal and a negative-phase clock signal of the differential clock signals output from the bias adjusting circuits,
• wherein the (2k-1)th bias adjusting circuit or the 2kth bias adjusting circuit adjust the DC bias voltage of a positive-phase clock signal or a negative-phase clock signal of the input differential clock signals and output the positive-phase clock signal and the negative-phase clock signal with an adjusted DC bias voltage such that a duty ratio becomes (2N-2k+1):(2k-1),
• wherein where k is an integer equal to or greater than 1 and equal to or less than N,
• wherein the duty ratio is a ratio between a period in which the positive-phase clock signal is High as to the negative-phase clock signal and a period in which the positive-phase clock signal is Low as to the negative-phase clock signal, and
• wherein the positive-phase clock signal output from the (2k-1)th bias adjusting circuit is input to the positive-phase clock input terminal of the (2k-1)th sampling circuit and the negative-phase clock input terminal of the 2kth sampling circuit, and the negative-phase clock signal output from the 2kth bias adjusting circuit is input to the negative-phase clock input terminal of the (2k-1)th sampling circuit and the positive-phase clock input terminal of the 2kth sampling circuit.

A track-and-hold circuit, comprising:

• N bias adjusting circuits each configured to adjust a DC bias voltage of an input clock signal, wherein N is an integer equal to or more than 2;
• and
• 2N sampling circuits each including a signal input terminal, a signal output terminal, a positive-phase clock input terminal, and a negative-phase clock input terminal second clock input terminal, each of the 2N sampling circuits being configured to switch between:
• a track mode in which an output signal output from the signal output terminal tracks an input signal input to the signal input terminal;
• and
• a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with the clock signal output from a respective one of the bias adjusting circuits and an externally input DC voltage;
• wherein a kth bias adjusting circuit adjusts the DC bias voltage of the input clock signal and outputs a kth clock signal with an adjusted DC bias voltage such that a duty ratio becomes (2N-2k+1):(2k-1);
• wherein the duty ratio is a ratio between a period in which the kth clock signal is High as to a kth externally input DC voltage and a period in which the kth clock signal is Low as to the kth externally input DC voltage;
• and
• wherein the kth clock signal output from the kth bias adjusting circuit is input to the positive-phase clock input terminal of the (2k-1)th sampling circuit and the negative-phase clock input terminal of the 2kth sampling circuit, and the kth externally input DC voltage is input to the negative-phase clock input terminal of the (2k-1)th sampling circuit and the positive-phase clock input terminal of the 2kth sampling circuit.

A track-and-hold circuit, comprising:

• N bias adjusting circuits each configured to adjust a DC bias voltage of an input clock signal, wherein N is an integer equal to or more than 2;
• 2N sampling circuits each including a signal input terminal, a signal output terminal, a positive-phase clock input terminal and a negative-phase clock input terminal second clock input terminal, each of the 2N sampling circuits being configured to switch between:
• a track mode in which an output signal output from the signal output terminal tracks an input signal input to the signal input terminal;
• and
• a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with the clock signal output from respective one of the bias adjusting circuits and an externally input DC voltage, and
• N comparators of which one each is interposed between the kth bias adjusting circuit and the (2k-1)th and 2kth sampling circuits, and that are differential-input differential-output type comparators that take as input the kth clock signal output from the kth bias adjusting circuit and the kth DC voltage that is externally input,
• wherein a kth bias adjusting circuit adjusts the DC bias voltage of the input clock signal and outputs a kth clock signal with an adjusted DC bias voltage such that a duty ratio becomes (2N-2k+1):(2k-1);
• wherein k is an integer equal to or greater than 1 and equal to or less than N;
• wherein the duty ratio is a ratio between a period in which the kth clock signal is High as to a kth externally input DC voltage and a period in which the kth clock signal is Low as to the kth externally input DC voltage;
• and
• wherein a kth positive-phase clock signal output from the kth comparator is input to a positive-phase clock input terminal of the (2k-1)th sampling circuit and a negative-phase clock input terminal of the 2kth sampling circuit, and a kth negative-phase clock signal output from the kth comparator is input to a negative-phase clock input terminal of the (2k-1)th sampling circuit and a positive-phase clock input terminal of the 2kth sampling circuit.