Multi-Channel Interleaved Analog-to-Digital Converter (ADC) using Overlapping Multi-Phase Clocks with SAR-Searched Input-Clock Delay Adjustments and Background Offset and Gain Correction

An overlapping-clock interleaved Analog-to-Digital Converter (ADC) comprising:

• a plurality of N channels, wherein N is a whole number of at least 3;
• an overlapping multi-phase clock input for receiving a plurality of channel sampling clocks having active pulses that overlap active pulses of channel sampling clocks for other channels in the plurality of N channels;
• wherein each of the plurality of N channels receives a channel sampling clock in the plurality of channel sampling clocks;
• wherein the channel sampling clock for a channel in the plurality of N channels has a different phase offset than other channel sampling clocks for other channels in the plurality of N channels, each channel sampling clock having an active pulse that overlaps active pulses of channel sampling clocks for adjacent channels in the plurality of N channels;
• wherein each channel comprises:
• an ADC having a sampled analog input and a digital output;
• a sampling switch between an analog input and the sampled analog input, the sampling switch responsive to a delayed clock;
• a Successive-Approximation-Register (SAR) that stores a delay setting;
• and
• a delay element generating a variable delay between the delayed clock and a channel sampling clock received from the overlapping multi-phase clock input, wherein the variable delay is determined by the delay setting in the SAR.

An interleaved Analog-to-Digital Converter (ADC) with overlapping multi-phase clocks comprising:

• an analog input;
• a plurality of channels;
• a buffer tree of analog buffers that receive the analog input and generate a plurality of analog input signals to the plurality of channels;
• a clock generator that generates a plurality of channel clocks each having a different phase and a same frequency and a same active pulsewidth, wherein an active pulsewidth for a channel overlap with the active pulsewidth of a previous channel and overlaps with the active pulsewidth of a following channel in an interleave order of the plurality of channels;
• wherein each channel further comprises:
• a channel ADC having a sampled analog input and a digital output;
• a sampling switch between an analog input signal in the plurality of analog input signals and the sampled analog input, the sampling switch responsive to a delayed clock;
• a Successive-Approximation-Register (SAR) that stores a delay setting for the channel;
• and
• a delay element adding a variable delay to a channel clock received from the clock generator to generate a delayed clock, wherein the variable delay is determined by the delay setting in the SAR;
• a bootstrapper for boosting an active voltage of the delayed clock that is generated by the delay element in response to the active pulsewidth of the channel clock, the bootstrapper applying a boosted voltage to the sampling switch.
• a channel correlator for correlating the digital output from the channel to digital outputs from adjacent channels in the plurality of channels to generate a correlation sign bit for the channel;
• and
• a calibrator, using the correlation sign bit to decide when to add a test bit to the SAR for a channel, and when to remove the test bit from the SAR for the channel, wherein each correlation sign bit is for adding or removing a test bit from a SAR in a different channel in the plurality of channels.