Increased phase interpolator linearity in phase-locked loop

A phase-locked loop (PLL) circuit comprising:

• a first phase detector to receive an in-phase reference clock and an in-phase feedback clock;
• a second phase detector to receive a quadrature reference clock and a quadrature feedback clock;
• a first variable current source to convert a first phase error received from the first phase detector into first current pulses;
• a second variable current source to convert a second phase error received from the second phase detector into second current pulses;
• an integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses;
• a ring oscillator to be driven by the current output signal;
• an in-phase phase interpolator (PI) coupled to an output of the ring oscillator, the in-phase PI to generate the in-phase feedback clock;
• and
• a quadrature PI coupled to the output of the ring oscillator, the quadrature PI to generate the quadrature feedback clock.

A system comprising:

• feed-forward clock circuitry to provide a receiver (RX) clock to a sampler circuit that is to sample a data lane of a set of RX data lanes, the RX clock comprising an in-phase reference clock and a quadrature reference clock;
• and
• an RX phase-locked loop coupled between the feed-forward clock circuitry and the sampler circuit, the RX PLL comprising:
• a first phase detector to receive the in-phase reference clock and an in-phase feedback clock, the first phase detector to output a first phase error;
• a second phase detector to receive the quadrature reference clock and a quadrature feedback clock, the second phase detector to output a second phase error;
• a first variable current source to convert the first phase error to first current pulses;
• a second variable current source to convert the second phase error to second current pulses;
• an integrator circuit coupled to the first variable current source and the second variable current source, the integrator circuit to sum, within a current output signal, the first current pulses and the second current pulses;
• a ring oscillator to be driven by the current output signal;
• and
• a pair of phase interpolators coupled to an output of the ring oscillator, the pair of phase interpolators to respectively generate the in-phase feedback clock and the quadrature feedback clock.