Digitally controlled delay line circuit and method

A digitally controlled delay line (DCDL) comprising:

• an input terminal;
• an output terminal;
• and
• a plurality of stages configured to propagate a signal along a first signal path from the input terminal to a selectable return stage of the plurality of stages, and along a second signal path from the return stage of the plurality of stages to the output terminal, each stage of the plurality of stages comprising:
• a first inverter configured to selectively propagate the signal along the first signal path;
• a second inverter configured to selectively propagate the signal along the second signal path;
• and
• a third inverter configured to selectively propagate the signal from the first signal path to the second signal path,
• wherein at least one of the first or third inverters comprises:
• a first p-type transistor and a first n-type transistor, each of the first p-type transistor and the first n-type transistor comprising a gate configured to receive the signal;
• and
• a tuning portion coupled between the first p-type transistor and the first n-type transistor, the tuning portion comprising either:
• a parallel configuration of independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor;
• or
• a parallel configuration of independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.

A method of controlling a signal delay time, the method comprising:

• receiving an input signal at a first stage of a plurality of sequentially coupled stages of a digitally controlled delay line (DCDL);
• and
• selecting a second stage of the plurality of sequentially coupled stages as a return stage, thereby activating a first tunable inverter of the second stage,
• wherein the activating the first tunable inverter of the second stage comprises activating one of:
• a parallel configuration of independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or
• a parallel configuration of independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.