Oxide thin film transistor, display panel and preparation method thereof

A display panel, comprising:

• a substrate;
• a driving circuit layer disposed on one side of a substrate, and the driving circuit layer comprises a first active layer, a first gate insulating layer disposed on one side of the first active layer away from the substrate, a first gate disposed on one side of the first gate insulating layer away from the substrate, a first interlayer insulating layer disposed on one side of the first gate away from the substrate, and a source/drain layer disposed on one side of the first interlayer insulating layer away from the substrate, wherein the source/drain layer comprises a first source and a first drain;
• wherein the first active layer comprises a first source doped region, a first channel region, a first drain doped region, a first diffusion region between the first source doped region and the first channel region, and a second diffusion region between the first drain doped region and the first channel region;
• wherein the first source is electrically connected to the first source doped region, and the first drain is electrically connected to the first drain doped region;
• each thickness of the first gate insulating layer corresponding to the first source doped region, the first drain doped region, the first diffusion region, and the second diffusion region is less than a thickness corresponding to the first channel region;
• and
• thicknesses of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region are both different from a thickness corresponding to the first source doped region and the first drain doped region.

A method for preparing a display panel, the display panel comprises a substrate and a drive circuit layer on one side of the substrate, wherein the method comprises:

• step S1:
• providing a substrate, and forming at least a first active layer, a first gate insulating layer, a first gate layer, and a photoresist layer on the substrate;
• wherein the first active layer comprises a first source doped region, a first channel region, a first drain doped region, a first diffusion region between the first source doped region and the first channel region, and a second diffusion region between the first drain doped region and the first channel region;
• step S2:
• patterning the photoresist layer to form a first photoresist pattern that does not block the first source doped region and the first drain doped region of the first active layer;
• step S3:
• etching the first gate layer and the first gate insulating layer by using the first photoresist pattern as a barrier layer, so that both thicknesses of the first gate insulating layer corresponding to the first source doped region and the first drain doped region are smaller than a thickness corresponding to the first diffusion region, the second diffusion region, and the first channel region;
• and simultaneously doping a conductive particle from the first gate insulating layer to the first source doped region and the first drain doped region;
• step S4:
• patterning the first photoresist pattern to form a second photoresist pattern, etching the first gate layer and the first gate insulating layer by using the first photoresist pattern as a barrier layer again, so that each thickness of the first gate insulating layer corresponding to the first diffusion region and the second diffusion region is less than a thicknesses corresponding to the first channel region;
• and stripping the second photoresist pattern;
• and
• step S5:
• forming an interlayer insulating layer on the first gate insulating layer, and forming a first source and a first drain on the interlayer insulating layer, wherein the first source and the first drain are electrically connected to the first source doped region and the first drain doped region through a source contact hole and a drain contact hole, respectively.