Semiconductor device including contact plug

A semiconductor device comprising:

• a semiconductor substrate provided with an active region;
• an isolation layer defining the active region on the semiconductor substrate;
• a gate trench intersecting the active region and extending to the isolation layer;
• a gate structure filling the gate trench and extending in a first direction parallel to an upper surface of the semiconductor substrate;
• an insulating barrier structure disposed on the active region, the isolation layer, and the gate structure;
• a bitline extending in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate, and disposed at a level higher than a level of the insulating barrier structure;
• and
• a first contact plug between the bitline and a first portion of the active region,
• wherein:
• the insulating barrier structure is disposed under the bitline;
• the insulating barrier structure comprises:
• a pair of first barrier patterns spaced apart from each other in the second direction, and
• a pair of second barrier patterns spaced apart from each other in the first direction;
• the pair of first barrier patterns are disposed between the pair of second barrier patterns;
• and
• the first contact plug is disposed between the pair of first barrier patterns.

A semiconductor device comprising:

• a semiconductor substrate provided with a plurality of active regions;
• an isolation layer defining each of the plurality of active regions on the semiconductor substrate;
• a plurality of gate trenches intersecting the plurality of active regions and extending to the isolation layer;
• a plurality of gate structures filling the plurality of gate trenches, respectively, and extending in a first direction parallel to an upper surface of the semiconductor substrate;
• a first impurity region and a second impurity region disposed in each of the plurality of active regions and spaced apart from each other;
• an insulating barrier structure disposed on the plurality of active regions, the isolation layer, and the plurality of gate structures;
• a bitline extending in a second direction perpendicular to the first direction and parallel to the upper surface of the semiconductor substrate, and disposed at a level higher than a level of where the insulating barrier structure is disposed;
• a first contact plug between the first impurity region and the bitline;
• a pad layer on the second impurity region;
• and
• a second contact plug on the pad layer,
• wherein the insulating barrier structure comprises:
• a pair of first barrier patterns extending in the first direction parallel to each other, and overlapping the plurality of gate structures;
• and
• a pair of second barrier patterns parallel to each other and extending in a first diagonal direction between the first direction and the second direction and parallel to the upper surface of the semiconductor substrate, and
• wherein the first contact plug is disposed in a region defined by the pair of first barrier patterns and the pair of second barrier patterns.