Transistor Isolation Regions and Methods of Forming the Same

A device comprising:

• a first insulating fin comprising a first lower insulating layer and a first upper insulating layer, the first upper insulating layer comprising a first dielectric material;
• a first gate structure extending along a sidewall of the first lower insulating layer and along a top surface of the first upper insulating layer;
• a second insulating fin comprising a second lower insulating layer and a second upper insulating layer, the second upper insulating layer comprising a second dielectric material, the second dielectric material different from the first dielectric material;
• and
• a second gate structure extending along a sidewall of the second lower insulating layer and along a top surface of the second upper insulating layer.

A method comprising:

• patterning a multi-layer stack to form a first trench between first nanostructures and to form a second trench between second nanostructures, the first trench wider than the second trench;
• depositing a first dielectric layer in the first trench and the second trench, the first dielectric layer comprising a first dielectric material;
• converting a first portion of the first dielectric layer at a first bottom of the first trench to a second dielectric material, a second portion of the first dielectric layer at a second bottom of the second trench remaining as the first dielectric material;
• and
• removing portions of the first dielectric layer above the first nanostructures and the second nanostructures to form a first insulating fin in the first trench and to form a second insulating fin in the second trench.