# US 2023/0154979 A1 · Method of manufacturing semiconductor devices and semiconductor devices

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- Number: US 2023/0154979 A1
- Document ID: US20230154979A1
- Status: Published application
- Kind: A1
- Application number: 18/097,073
- Filed: 2023-01-13
- Published: 2023-05-18
- Earliest claimed: 2020-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company , Ltd
- Inventors: Shahaji B. MORE; chandrashekhar Prakash SAVANT
- Web page: https://patentgrep.com/patent/US20230154979A1

## CPC

- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10B 10/12: {comprising a MOSFET load element}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A gate structure of a field effect transistor includes a first gate dielectric layer, a second gate dielectric layer, and one or more conductive layers disposed over the first gate dielectric layer and the second gate dielectric layer. The first gate dielectric layer is separated from the second gate dielectric layer by a gap filled with a diffusion blocking layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a first gate dielectric layer in a gate space, the gate space being laterally surrounded by one or more insulating layers;
forming a second gate dielectric layer over the first gate dielectric layer;
separating the first and second gate dielectric layers into a first stacked gate dielectric layer and a second stacked gate dielectric layer by forming a trench;
forming one or more work function adjustment material (WFM) layers over the first stacked gate dielectric layer and the second stacked gate dielectric layer; and
forming a body gate electrode layer over the one or more WFM layers.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the first gate dielectric layer comprises a first region and a second region adjacent to the first region,
at least one of the first region or the second region includes a dopant,
a dopant concentration is different in the first region than the second region, and
the first stacked gate dielectric layer includes the first region and the second stacked gate dielectric layer includes the second region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu, Pb, Tr, Nd, Gd, Pm, Pr, Ho, Er, Tm, Sm, Yb, Al, Nb, Mo, W, Ti, Hf, Zr, Ta, V, Ba and Mg.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first and second gate dielectric layers include one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide, respectively.

### Claim 5 (depends on 1)

The method of claim 1, wherein the trench is filled by a part of the one or more WFM layers.

### Claim 6 (depends on 1)

The method of claim 1, wherein the separating the first and second gate dielectric layers comprises:
forming a hard mask layer over the second gate dielectric layer;
forming a mask pattern having an opening over the hard mask layer;
patterning the hard mask layer by using the mask pattern as an etching mask;
patterning the second and first gate dielectric layers by using at least one of the mask pattern or the patterned hard mask layer as an etching mask; and
removing the mask pattern and the patterned hard mask layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the hard mask layer is made of a different material than the first and second gate dielectric layers and includes at least one selected from the group consisting of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium oxynitride, titanium nitride, and tantalum oxynitride.

### Claim 8 (depends on 7)

The method of claim 7, wherein a thickness of the hard mask layer is in a range from 0.5 nm to 20 nm.

### Claim 9 (depends on 6)

The method of claim 6, wherein the mask pattern is made of an organic antireflective coating material.

### Claim 10

A method of manufacturing a semiconductor device, comprising:
forming a first gate dielectric layer over a first channel region made of a first semiconductor material and over an isolation insulating layer;
forming a second gate dielectric layer over a second channel region made of a second semiconductor material and over the isolation insulating layer, the first gate dielectric layer being laterally in contact with the second gate dielectric layer at a boundary located over the isolation insulating layer;
forming a third gate dielectric layer over the first and second gate dielectric layers;
separating, by using a patterning operation, the third gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer by a trench; and
forming a diffusion barrier by filling the trench with a dielectric material or a conductive material, wherein:
at least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, and
a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first and second gate dielectric layers includes hafnium oxide.

### Claim 12 (depends on 11)

The method of claim 11, wherein the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb.

### Claim 13 (depends on 10)

The method of claim 10, wherein the third gate dielectric layer include one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium-zirconium oxide, respectively.

### Claim 14 (depends on 13)

The method of claim 13, wherein the third gate dielectric layer is made of a different material than the first and second gate dielectric layers.

### Claim 15 (depends on 10)

The method of claim 10, wherein a width of the trench is in a range from 10 nm to 150 nm.

### Claim 16 (depends on 10)

The method of claim 10, wherein the diffusion barrier includes at least one layer of TiAl, TiAlC, TaAl, TaAlC, TiN, TiSiN, Ru, WN, WCN, MoN or TaN.

### Claim 17

A method of manufacturing a semiconductor device, comprising:
forming a pair of first gate spaces and a pair of second gate spaces;
forming a first gate dielectric layer in the pair of first gate spaces and a second gate dielectric layer in the pair of second gate spaces;
forming a third gate dielectric layer over the first and second gate dielectric layers;
separating, by using a patterning operation, the third gate dielectric layer the first gate dielectric layer and the second gate dielectric layer by a trench that connects the pair of first gate spaces and the pair of second gate spaces; and
forming one or more work function adjustment material (WFM) layers over the third gate dielectric layer in the pair of first gate spaces and over the third gate dielectric layer in the pair of second gate spaces; and
forming a body gate electrode layer over the one or more WFM layers,
wherein a part of the one or more WFM layers fills the trench.

### Claim 18 (depends on 17)

The method of claim 17, wherein:
at least one of the first gate dielectric layer or the second gate dielectric layer includes a dopant, and
a dopant concentration is different between the first gate dielectric layer and the second gate dielectric layer.

### Claim 19 (depends on 18)

The method of claim 18 wherein the dopant is at least one selected from the group consisting of La, Sc, Sr, Ce, Y, Dy, Eu and Yb.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first, second and third dielectric layers each include one selected from the group consisting of one or more of aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide and titanium oxynitride.