# US 2023/0154931 A1 · Displays With Silicon and Semiconducting Oxide Thin-Film Transistors

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- Number: US 2023/0154931 A1
- Document ID: US20230154931A1
- Status: Published application
- Kind: A1
- Application number: 18/155,828
- Filed: 2023-01-18
- Published: 2023-05-18
- Earliest claimed: 2013-08-26
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Hiroshi Osawa; Kyung-Wook Kim; Ming-Chin Hung; Shih Chang Chang; Yu-Cheng Chen
- Web page: https://patentgrep.com/patent/US20230154931A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/13624: {having more than one switching element per pixel}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- H10K 59/1213: {the pixel elements being TFTs}
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- G02F 1/13452: {Conductors connecting driver circuitry and terminals of panels}
- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/13685: {Top gates}
- G02F 2202/104: poly-Si
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

An electronic device may include a display having an array of display pixels on a substrate. The display pixels may be organic light-emitting diode display pixels or display pixels in a liquid crystal display. In an organic light-emitting diode display, hybrid thin-film transistor structures may be formed that include semiconducting oxide thin-film transistors, silicon thin-film transistors, and capacitor structures. The capacitor structures may overlap the semiconducting oxide thin-film transistors. Organic light-emitting diode display pixels may have combinations of oxide and silicon transistors. In a liquid crystal display, display driver circuitry may include silicon thin-film transistor circuitry and display pixels may be based on oxide thin-film transistors. A single layer or two different layers of gate metal may be used in forming silicon transistor gates and oxide transistor gates. A silicon transistor may have a gate that overlaps a floating gate structure.

## Claims

### Claim 1

A display having an array of pixels, the display comprising:
a substrate;
thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, and wherein the oxide transistor comprises a semiconducting oxide layer and a second gate; and
a light shield that is interposed between the substrate and at least one of the silicon transistor and the oxide transistor.

### Claim 2 (depends on 1)

The display defined in claim 1, further comprising:
a buffer layer formed between the substrate and the thin-film transistor structures.

### Claim 3 (depends on 2)

The display defined in claim 2, wherein the polysilicon channel is interposed between the buffer layer and the first gate.

### Claim 4 (depends on 2)

The display defined in claim 2, wherein the semiconducting oxide layer is interposed between the buffer layer and the second gate.

### Claim 5 (depends on 2)

The display defined in claim 2, wherein the buffer layer is interposed between the light shield and the silicon transistor.

### Claim 6 (depends on 2)

The display defined in claim 2, wherein the buffer layer is formed from an inorganic material.

### Claim 7 (depends on 1)

The display defined in claim 1, further comprising:
a gate insulator layer that is interposed between the polysilicon channel and the first gate.

### Claim 8 (depends on 1)

The display defined in claim 1, further comprising:
a dielectric layer, wherein the first gate is interposed between the dielectric layer and the polysilicon channel.

### Claim 9 (depends on 1)

The display defined in claim 1, wherein the substrate is a polymer substrate.

### Claim 10 (depends on 1)

The display defined in claim 1, wherein the light shield is interposed between the substrate and the silicon transistor.

### Claim 11 (depends on 1)

The display defined in claim 1, further comprising:
an electrode for one of the pixels, wherein the electrode is electrically connected to the semiconducting oxide layer.

### Claim 12 (depends on 11)

The display defined in claim 11, further comprising:
at least one dielectric layer that is interposed between the electrode and the semiconducting oxide layer.

### Claim 13 (depends on 12)

The display defined in claim 12, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer and wherein a layer of metal is interposed between the first dielectric layer and the second dielectric layer.

### Claim 14 (depends on 13)

The display defined in claim 13, wherein a first metal via portion electrically connects the layer of metal to the semiconducting oxide layer and wherein a second metal via portion electrically connects the layer of metal to the electrode.

### Claim 15 (depends on 14)

The display defined in claim 14, wherein the first and second dielectric layers are first and second organic dielectric layers.

### Claim 16

A display comprising:
a substrate;
a buffer layer formed over the substrate;
thin-film transistor structures, wherein the buffer layer is interposed between the substrate and the thin-film transistor structures, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, wherein the polysilicon channel is interposed between the buffer layer and the first gate, wherein the oxide transistor comprises a semiconducting oxide layer and a second gate, and wherein the semiconducting oxide layer is interposed between the buffer layer and the second gate; and
a light shield that is interposed between the substrate and the buffer layer, wherein the light shield overlaps at least one of the silicon transistor and the oxide transistor.

### Claim 17 (depends on 16)

The display defined in claim 16, wherein the light shield overlaps the silicon transistor.

### Claim 18 (depends on 16)

The display defined in claim 16, wherein the buffer layer is formed from an inorganic dielectric material.

### Claim 19 (depends on 16)

The display defined in claim 16, further comprising:
a planarization layer that is formed over the thin-film transistor structures.

### Claim 20

A display having an array of pixels, the display comprising:
a substrate;
thin-film transistor structures for the array of pixels, wherein the thin-film transistor structures include a silicon transistor and an oxide transistor, wherein the silicon transistor comprises a polysilicon channel and a first gate, wherein the oxide transistor comprises a semiconducting oxide layer and a second gate;
a light shield that is interposed between the substrate and at least one of the silicon transistor and the oxide transistor;
a buffer layer formed between the substrate and the thin-film transistor structures;
an electrode that is electrically connected to the semiconducting oxide layer; and
at least one dielectric layer that is interposed between the electrode and the semiconducting oxide layer, wherein the at least one dielectric layer comprises a first dielectric layer and a second dielectric layer and wherein a layer of metal is interposed between the first dielectric layer and the second dielectric layer.