Integration of Multiple Transistors Having Fin and Mesa Structures

A structure comprising:

• a bulk semiconductor substrate;
• a first plurality of dielectric isolation regions over the bulk semiconductor substrate;
• a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions;
• a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins;
• a second plurality of dielectric isolation regions over the bulk semiconductor substrate;
• a first mesa structure in the second plurality of dielectric isolation regions;
• and
• a second gate stack over the first mesa structure, wherein top surfaces of the first gate stack and the second gate stack are coplanar with each other.

A structure comprising:

• a bulk semiconductor substrate;
• a Fin Field Effect Transistor (FinFET) comprising:
• a plurality of semiconductor fins over the bulk semiconductor substrate;
• and
• a first gate dielectric on top surfaces and sidewalls of the plurality of semiconductor fins, wherein the first gate dielectric has a first thickness;
• a medium-voltage transistor comprising:
• a first mesa structure over the bulk semiconductor substrate;
• and
• a second gate dielectric on a first top surface of the first mesa structure, wherein the second gate dielectric has a second thickness greater than the first thickness;
• and
• a high-voltage transistor comprising:
• a second mesa structure over the bulk semiconductor substrate;
• and
• a third gate dielectric on a second top surface of the second mesa structure, wherein the third gate dielectric has a third thickness greater than the second thickness.