Semiconductor package

A semiconductor package comprising:

• a package base substrate including a potential plate;
• an interposer arranged on the package base substrate and comprising at least one interposer through electrode, at least one first connection bump, and at least one second connection bump;
• a first stacked chip unit arranged on the interposer and comprising a first semiconductor chip and at least one second semiconductor chip arranged on the first semiconductor chip;
• a second stacked chip unit arranged on the interposer and comprising at least one third semiconductor chip arranged to be spaced apart from the first stacked chip unit in a horizontal direction parallel to an upper surface of the package base substrate;
• and
• a plurality of passive device units arranged on the package base substrate and arranged to be spaced apart from the first stacked chip unit and the second stacked chip unit in the horizontal direction,
• wherein the interposer comprises a plurality of interposer through electrodes that vertically penetrate the interposer,
• the at least one first connection bump is a dummy bump,
• in a plan view, the plurality of passive device units surround the at least one first connection bump, and
• the potential plate electrically connects the at least one first connection bump and a power terminal of the plurality of passive device units to each other.

A semiconductor package comprising:

• a package base substrate comprising a plurality of interconnection layers;
• an interposer arranged on the package base substrate and comprising a plurality of interposer through electrodes, a plurality of first connection bumps, and a plurality of second connection bumps;
• a first stacked chip unit arranged on the interposer and comprising a first semiconductor chip and at least one second semiconductor chip arranged on the first semiconductor chip;
• a second stacked chip unit arranged on the interposer and comprising at least one third semiconductor chip arranged to be spaced apart from the first stacked chip unit in a horizontal direction;
• and
• a plurality of passive device units arranged on the package base substrate and arranged to be spaced apart from the first stacked chip unit and the second stacked chip unit in the horizontal direction,
• wherein the plurality of interposer through electrodes and the plurality of second connection bumps are electrically connected to each other,
• each of the plurality of first connection bumps is a dummy bump,
• the first semiconductor chip comprises a buffer chip that controls the second semiconductor chip,
• the at least one second semiconductor chip comprises a memory cell chip,
• the at least one third semiconductor chip comprises a memory cell chip and a logic chip,
• each of the plurality of passive device units comprises a capacitor,
• in a plan view, the plurality of passive device units surrounds the plurality of first connection bumps,
• the plurality of first connection bumps and the plurality of passive device units are electrically connected to each other through a potential plate of the package base substrate,
• the potential plate is arranged on an uppermost interconnection layer among the plurality of interconnection layers,
• the potential plate is arranged on a single interconnection layer, and
• the potential plate comprises a power path.