Semiconductor chip including align mark protection pattern and semiconductor package including semiconductor chip including the align mark protection pattern

A semiconductor chip comprising:

• a chip body;
• a redistribution layer pattern and an alignment mark pattern that are disposed to be spaced apart from each other on a surface of the chip body;
• an insulating pattern disposed on the redistribution layer pattern;
• and
• an alignment mark protection pattern disposed on the alignment mark pattern,
• wherein the alignment mark protection pattern includes a metal material, and
• wherein the alignment mark protection pattern offsets a height difference between the alignment mark pattern and the insulating pattern.

A semiconductor package comprising:

• a package substrate;
• and
• a semiconductor chip mounted over the package substrate and including an alignment mark pattern for alignment of the semiconductor chip over the package substrate,
• wherein the semiconductor chip comprises:
• a chip body;
• a redistribution layer pattern disposed on a surface of the chip body;
• an alignment mark pattern disposed to be spaced apart from the redistribution layer pattern on the surface of the chip body;
• a first insulating pattern disposed to contact a side surface of the redistribution layer pattern and a side surface of the alignment mark pattern on the surface of the chip body;
• a second insulating pattern disposed on the redistribution layer pattern to protect the redistribution layer pattern;
• and
• an alignment mark protection pattern disposed on the alignment mark pattern and offsetting a height difference between the second insulating pattern and the alignment mark pattern.