Bottom dielectric isolation integration with buried power rail

A semiconductor device, comprising:

• a protective liner on a support pillar;
• a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail;
• a source/drain on a second portion of the protective liner, wherein the support pillar is on an opposite side of the second portion of the protective liner from the source/drain;
• a plurality of nanochannels on the second portion of the protective liner, wherein the source/drain is in electrical contact with the plurality of nanochannels;
• and
• a source/drain contact on the source/drain and in electrical communication with the buried power rail.

A method of forming a semiconductor device, comprising:

• forming a separation trench through a stack of alternating nanosheet sections and sacrificial sections, a first sacrificial section, and into an underlying substrate mesa to form a stack of alternating nanosheet channels and sacrificial segments on a first sacrificial segment and a support pillar having a sidewall;
• removing the first sacrificial section to form a first cavity;
• forming a protective liner in the first cavity and on the sidewall of the support pillar;
• forming a buried power rail on a first portion of the protective liner;
• removing the sacrificial sections;
• forming a source/drain on a second portion of the protective liner;
• and
• forming a source/drain contact electrically connecting the source/drain to the buried power rail.