US 2023/0154751 A1 · FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIRCUIT COMPONENTS

Abstract

A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

Claims20

Dependent claims

A method for forming an integrated circuit, the method comprising:

forming a first spacer on sidewalls of a first trench in a hardmask that is on a dielectric layer;
patterning the dielectric layer using the hardmask and the first spacer as a mask to form a first channel having a cross-sectional area that is smaller than a cross-sectional area of the first trench;
forming a second spacer on sidewalls of a second trench in the hardmask;
patterning the dielectric layer using the hardmask and the second spacer as a mask to form a second channel having a cross-sectional area that is smaller than a cross-sectional area of the second trench;
removing the hardmask, the first spacer, and the second spacer;
depositing a metal into the first channel and the second channel in the dielectric layer;
and
performing a double patterning pitch splitting process including a plurality of mask-exposures used to form a plurality of conductors that electrically couple to at least the first channel and the second channel.

5 more elements

A method for forming an integrated circuit, the method comprising:

depositing a dielectric layer on a substrate;
depositing a first hardmask on the dielectric layer;
depositing a second hardmask on the first hardmask;
patterning the second hardmask to form a first trench in the second hardmask;
depositing a first spacer material on the second hardmask and in the first trench;
partially etching the first spacer material so as to leave a first spacer on sidewalls of the first trench;
patterning the first hardmask using the second hardmask and the first spacer as a mask to form a first trench extension having a cross-section that is smaller than a cross-section of the first trench;
patterning the second hardmask to form a second trench in the second hardmask;
depositing a second spacer material on the second hardmask and in the second trench;
partially etching the second spacer material so as to leave a second spacer on sidewalls of the second trench;
patterning the first hardmask using the second hardmask and the second spacer as a mask to form a second trench extension having a cross-section that is smaller than a cross-section of the second trench;
removing the first spacer and the second spacer;
removing the second hardmask;
patterning the dielectric layer using the first hardmask, the first trench extension, and the second trench extension to form a first channel and a second channel in the dielectric layer;
depositing metal on the dielectric layer and in the first channel and the second channel;
and
removing the metal on the dielectric layer and leaving the metal in the first channel and the second channel.

14 more elements

A system comprising:

a memory storing instructions for performing a patterning technique to form an integrated circuit;
and
a processor, coupled with the memory and to execute the instructions that, when executed, cause the processor to perform operations including:
forming a first spacer on sidewalls of a first trench in a hardmask that is on a dielectric layer;
patterning the dielectric layer using the hardmask and the first spacer as a mask to form a first channel having a cross-sectional area that is smaller than a cross-sectional area of the first trench;
forming a second spacer on sidewalls of a second trench in the hardmask;
patterning the dielectric layer using the hardmask and the second spacer as a mask to form a second channel having a cross-sectional area that is smaller than a cross-sectional area of the second trench;
removing the hardmask, the first spacer, and the second spacer;
depositing a metal into the first channel and the second channel in the dielectric layer;
and
performing a double patterning pitch splitting process including a plurality of mask-exposures used to form a plurality of conductors that electrically couple to at least the first channel and the second channel.

8 more elements

Dependencies are inferred from the claim text.

Fabrication technique for forming ultra-high density integrated circuit components

Life of this patent

Fabrication technique for forming ultra-high density integrated circuit components

Life of this patent

Abstract

Claims20