Memory device, method for programming memory device, program verification method and memory system

A method of programming a memory device, comprising:

• applying an (i+1)th programming pulse to to-be-programmed memory cells in the memory device;
• in a process of applying the (i+1)th programming pulse, counting fail bits in programming for an nth state and in programming for an (n+k)th state in an ith programming operation according to a verification result for an nth state and a verification result for an (n+k)th state in the ith programming operation, to obtain an ith count result, wherein programming states verified by the ith program verification operation range from the nth state to the (n+k)th state, i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to a highest programming state of the memory device;
• determining a range of programming states to be verified by an (i+1)th program verification operation according to the ith count result;
• and
• executing the (i+1)th program verification operation according to the determined range of the programming states to be verified by the (i+1)th program verification operation.

A memory device, comprising:

• a memory cell array comprising memory cell rows;
• word lines respectively coupled to the memory cell rows;
• and
• a peripheral circuit coupled to the word lines and configured to execute program verification operation on a selected memory cell row from the memory cell rows, the selected memory cell row coupled to a selected word line, wherein in order to execute the program verification operation, the peripheral circuit is configured to:
• obtain an ith verification result of an ith program verification operation, wherein programming states verified by the ith program verification operation range from an nth state to an (n+k)th state, i and n are positive integers, k is a natural number, and the (n+k)th state is less than or equal to a highest programming state of the memory device;
• determine a range of programming states to be verified by the (i+1)th program verification operation according to a verification sub-result for the nth state and a verification sub-result for the (n+k)th state in the ith verification result;
• and
• execute the (i+1)th program verification operation according to the determined range of programming states to be verified by the (i+1)th program verification operation.