Semiconductor package

A semiconductor package, comprising:

• a redistribution substrate;
• a semiconductor chip on a first surface of the redistribution substrate, the semiconductor chip including a chip pad electrically connected to the redistribution substrate;
• and
• a conductive terminal on a second surface, opposite the first surface, of the redistribution substrate,
• wherein the redistribution substrate includes:
• a first dielectric layer;
• a second dielectric layer in contact with the first dielectric layer;
• a first redistribution pattern in the first dielectric layer and the second dielectric layer;
• a second redistribution pattern in the second dielectric layer;
• and
• a insulative pattern formed in a first recess region of the first redistribution pattern,
• wherein the first redistribution pattern is interposed between and electrically connects the chip pad and the second redistribution pattern,
• wherein the first redistribution pattern, the second redistribution pattern and the insulative pattern are vertically overlapped.

A semiconductor package, comprising:

• a redistribution substrate;
• and
• a chip pad on the redistribution substrate, the chip pad electrically connects to the redistribution substrate;
• wherein the redistribution substrate includes:
• a first dielectric layer;
• a second dielectric layer in contact with the first dielectric layer;
• a third dielectric layer in contact with the second dielectric layer;
• a first redistribution pattern in the first dielectric layer and the second dielectric layer;
• a second redistribution pattern in the second dielectric layer and the third dielectric layer;
• and
• a first insulative pattern formed in a first recess region of the first redistribution pattern,
• wherein the first redistribution pattern is interposed between and electrically connects the chip pad and the second redistribution pattern,
• wherein each of the first to second redistribution pattern includes:
• a wire part on one surface of a corresponding one of the first to second dielectric layers, the wire part extending parallel to the one surface of the corresponding one of the first to second dielectric layers;
• and
• a via part that extends from the wire part and penetrates the corresponding one of the first to second dielectric layers,
• the first via part, the second via part and the first insulative pattern are vertically aligned.

A semiconductor package, comprising:

• a redistribution substrate;
• a semiconductor chip on a first surface of the redistribution substrate, the semiconductor chip including a chip pad electrically connected to the redistribution substrate;
• a molding layer that covers the semiconductor chip;
• and
• a conductive terminal on a second surface, opposite the first surface, of the redistribution substrate,
• wherein the redistribution substrate includes:
• a first dielectric layer;
• a second dielectric layer in contact with the first dielectric layer;
• a first redistribution pattern in the first dielectric layer and the second dielectric layer, the first redistribution pattern includes a first via part in the first dielectric layer and a first wire part in the second dielectric layer;
• a second redistribution pattern in the second dielectric layer, the second redistribution pattern includes a second via part in the second dielectric layer and a second wire part on the second dielectric layer;
• a insulative pattern formed in a first recess region of the first redistribution pattern;
• and
• an under-bump pattern adjacent to the conductive terminal and electrically connected to the conductive terminal,
• wherein the first redistribution pattern is interposed between and electrically connects the chip pad and the second redistribution pattern,
• wherein the first via part has a first center line that extends vertically while passing through a center of the first via part, the second via part has a second center line that extends vertically while passing through a center of the second via part and the insulative pattern has a third center line that extends vertically while passing through a center of the insulative pattern,
• wherein the first, second and third center lines are vertically aligned with each other.