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US 2023/0147765 A1Published application
Memory device having row decoder array architecture
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungyeon Kim, Jooyong Park, Hongsoo Jeon
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Abstract
A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
Claims20
A memory device comprising:
- a peripheral circuit structure;
- and
- a cell array structure vertically overlapping the peripheral circuit structure, wherein the cell array structure includes:
- a memory cell area including a plurality of word lines extending in a first horizontal direction;
- and
- a plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction,
- wherein the memory cell area includes a plurality of memory blocks separated from each other by a plurality of word line cut areas extending long in the first horizontal direction,
- wherein the memory cell area is divided into a normal cell area in which a plurality of normal memory blocks among the plurality of memory blocks are disposed, and a dummy cell area in which a plurality of dummy memory blocks among the plurality of memory blocks are disposed,
- wherein the plurality of dummy memory blocks include a bit line through-electrode area including a plurality of through electrodes respectively connected to the plurality of bit lines,
- wherein the plurality of through electrodes vertically extend into the peripheral circuit structure through the plurality of word lines,
- wherein the peripheral circuit structure includes a row decoder area in which a row decoder circuit for controlling a plurality of word lines of each memory block of the plurality of memory blocks of the normal cell area is disposed,
- wherein the row decoder area is adjacent to the plurality of memory blocks, and
- wherein the row decoder circuit includes:
- a first unit row decoder circuit being connected to n normal memory blocks among the plurality of normal memory blocks, n being a positive integer, and
- a second unit row decoder circuit being connected to (n−1) normal memory blocks among the plurality of normal memory blocks.
12 more elements
A memory device comprising:
- a peripheral circuit structure;
- and
- a cell array structure vertically overlapping the peripheral circuit structure, wherein the cell array structure includes:
- a memory cell area including a plurality of word lines extending in a first horizontal direction;
- a plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction;
- and
- a pair of dummy step areas disposed on opposite sides of the memory cell area, respectively,
- wherein the memory cell area includes a plurality of memory blocks separated from each other by a plurality of word line cut areas extending long in the first horizontal direction,
- wherein the memory cell area is divided into a normal cell area in which a plurality of normal memory blocks among the plurality of memory blocks are disposed, and a dummy cell area in which a plurality of dummy memory blocks among the plurality of memory blocks are disposed,
- wherein, in each dummy step area of the pair of dummy step areas, the plurality of word lines extend parallel to each other in the first horizontal direction and the second horizontal direction and vertically overlap each other in a stepwise manner,
- wherein the peripheral circuit structure includes a row decoder area in which a row decoder circuit for controlling a plurality of word lines of each memory block of the plurality of memory blocks of the normal cell area is disposed,
- wherein the row decoder area is adjacent to the plurality of memory blocks, wherein the row decoder circuit includes:
- a first unit row decoder circuit being connected to n normal memory blocks of the plurality of normal memory blocks, n being a positive integer, and
- a second unit row decoder circuit being connected to (n−1) first normal memory blocks of the plurality of normal memory blocks,
- wherein the second unit row decoder circuit is adjacent to an area in which a first dummy step area among the pair of dummy step areas and the (n−1) first normal memory blocks are disposed, and
- wherein a height, in the second horizontal direction, of the second unit row decoder circuit corresponds to a sum of block heights of the (n−1) first normal memory blocks and a height, in the second horizontal direction, of the first dummy step area.
13 more elements
A memory device comprising:
- a first chip including a memory cell area;
- a pair of dummy step areas disposed on opposite sides of the memory cell area;
- a first metal pad, wherein the memory cell area includes:
- a plurality of word lines extending in a first horizontal direction, and
- a plurality of bit lines extending in a second horizontal direction crossing the first horizontal direction,
- wherein the plurality of word lines extend parallel to each other in the first horizontal direction and the second horizontal direction and vertically overlap each other,
- wherein the memory cell area includes a plurality of memory blocks separated from each other by a plurality of word line cut areas extending long in the first horizontal direction, and
- wherein the memory cell area is divided into a normal cell area in which a plurality of normal memory blocks are disposed and a dummy cell area in which a plurality of dummy memory blocks are disposed;
- and
- a second chip including:
- a second metal pad, and
- a peripheral circuit area connected in a vertical direction to the memory cell area by the first and second metal pads connected with each other, wherein the peripheral circuit area includes a row decoder area in which a row decoder circuit for controlling a plurality of word lines of each memory block of the plurality of memory blocks of the normal cell area is disposed,
- wherein, when viewed in a plan view, the row decoder area is adjacent to the plurality of memory blocks,
- wherein the row decoder circuit includes:
- a first unit row decoder circuit connected to n normal memory blocks of the plurality of normal memory blocks, n being a positive integer, and
- a second unit row decoder circuit being connected to (n−1) first normal memory blocks of the plurality of normal memory blocks,
- wherein the second unit row decoder circuit is adjacent to an area where a first dummy step area among the pair of dummy step areas and the (n−1) first normal memory blocks are disposed,
- wherein a height, in the second horizontal direction, of the second unit row decoder circuit corresponds to a sum of block heights of the (n−1) first normal memory blocks and a height, in the second horizontal direction, of the first dummy step area, and
- wherein the height, in the second horizontal direction, of the first dummy step area is a distance between an edge of a lowermost word line among the plurality of word lines and an edge of an uppermost word line among the plurality of word lines.
16 more elements
Dependencies are inferred from the claim text.