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US 2023/0147746 A1Published application
Silicon carbide junction field effect transistors
AssigneePower Integrations, Inc.
InventorsKuo-Chang Robert YANG, Kamal Raj VARADARAJAN, Sorin S. GEORGESCU
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Abstract
Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (106). MET gate and MET source (108) may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).
Claims11
A silicon carbide (SiC) planar gate junction field effect transistor (JFET) comprising:
- an active cell comprising:
- a substrate layer;
- an epitaxial layer formed on the substrate layer;
- a shallow source implanted within the epitaxial layer;
- and
- a deep gate implanted below the shallow source so as to create a JFET neck within the epitaxial layer.
3 more elements
Dependencies are inferred from the claim text.