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US 2023/0147686 A1Published application
Nonvolatile sram
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPerng-Fei Yuh, Jui-Che Tsai, Hiroki Noguchi, Yih Wang
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Abstract
A memory device has a plurality of bit cells, each of which includes an SRAM cell having a storage node selectively connectable to a first bit line in response to a control signal received on a first word line. Each bit cell further includes an MRAM cell selectively connectable to the storage node of the SRAM cell in response to a control signal received on a second word line.
Claims20
A memory cell, comprising:
- an SRAM cell having a first storage node selectively connectable to a first bit line in response to a control signal received on a first word line, and a second storage node selectively connectable to a first bit line bar in response to the control signal received on the first word line;
- an MRAM cell including a first MTJ selectively connectable to the first storage node of the SRAM cell in response to a control signal received on a second word line, and a second MTJ selectively connectable to the second storage node of the SRAM cell in response to the control signal received on the second word line, wherein the first and second MTJs are connected to a second bit line MBL;
- wherein the second bit line is configured to receive an MRAM bit line control signal to connect a first terminal of the first MTJ and a first terminal of the second MTJ to a first voltage level, and thereafter the second word line is configured to receive an MRAM word line control signal to connect the first and second MTJs to the first and second storage nodes, respectively;
- and
- wherein the second bit line is configured to receive the MRAM bit line control signal to connect the first terminal of the first MTJ and the first terminal of the second MTJ to a second voltage level, and thereafter the second word line is configured to receive the MRAM word line control signal to connect the first and second MTJs to the first and second storage nodes, respectively.
2 more elements
A method, comprising:
- providing a memory bit cell including an SRAM cell and an MRAM cell;
- in response to a first event, writing data from a first storage node of the SRAM cell to a first MTJ of the MRAM cell;
- in response to the first event and after writing the data from the first storage node of the SRAM cell to the first MTJ of the MRAM cell, writing data from a second storage node of the SRAM cell to a second MTJ element of the MRAM cell;
- in response to a second event, writing data from the first MTJ of the MRAM cell to the first storage node of the SRAM cell, and writing data from the second MTJ element of the MRAM cell to the second storage node of the SRAM cell;
- and
- in response to the second event and after writing the data from the first MTJ of the MRAM cell to the first storage node of the SRAM cell and writing the data from the second MTJ element of the MRAM cell to the second storage node of the SRAM cell, electrically disconnecting the MRAM cell from the SRAM cell.
3 more elements
A method, comprising:
- connecting a free layer terminal of a first MTJ to a first voltage level;
- connecting a free layer terminal of a second MTJ to the first voltage level;
- connecting a pinned layer terminal of the first MTJ to a first storage node of an SRAM cell;
- connecting a pinned layer terminal of the second MTJ to a second storage node of the SRAM cell;
- connecting the free layer terminal of the first MTJ to a second voltage level;
- connecting the free layer terminal of the second MTJ to the second voltage level;
- connecting the pinned layer terminal of the first MTJ to the first storage node of the SRAM cell;
- and
- connecting the pinned layer terminal of the second MTJ to the second storage node of the SRAM cell.
6 more elements
Dependencies are inferred from the claim text.