Hardware-based artificial neural network device
AssigneesSeoul National University R&Db Foundation, Inha University Research and Business Foundation
InventorsByung-Gook PARK, Sungmin HWANG, Junsu YU, Hyungjin KIM
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Abstract
A hardware-based artificial neural network device includes a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight, a word line selection unit including a plurality of switching elements respectively connected to word lines of the synaptic array, a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array, and a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array.
Claims12
A hardware-based artificial neural network device comprising:
- a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight;
- a word line selection unit including a plurality of switching elements respectively connected to word lines of the synaptic array;
- a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array;
- and
- a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array.
A matrix calculation device comprising:
- a synaptic array including a plurality of capacitor-based synaptic cells, each having a variable capacitance according to a recorded weight;
- a word line selection unit including a plurality of switching elements respectively connected to word lines of the synaptic array;
- a bit line charging unit including a plurality of switching elements, each being connected to one end of each of bit lines of the synaptic array;
- a bit line discharging unit including a plurality of switching elements, each being connected to the other end of each of the bit lines of the synaptic array;
- and
- a control unit configured to control operations of the synaptic array, the word line selection unit, the bit line charging unit, and the bit line discharging unit.
Dependencies are inferred from the claim text.