Memory system, refresh control circuit, and refresh control method

A memory system, comprising:

• a memory device that includes a plurality of rows of memory cells;
• and
• a controller that controls the memory device,
• wherein the controller inputs the accessed rows of the plurality of the rows of the memory cells to a counting bloom filter, determines rows of the accessed rows as being frequently accessed as candidate rows, based on count values stored in the counting bloom filter, and controls the memory device to perform a target refresh operation on rows of the candidate rows that are adjacent to a determined target row.

A refresh control method of a plurality of rows of memory cells, the method comprising:

• obtaining a plurality of result values of a first hash operation by inputting an address of a first row of the plurality of rows of the memory cells into a plurality of hash control logics, and updating count values of corresponding counters of a plurality of counters that are respectively indicated by the plurality of result values of the first hash operation, in a counting period;
• obtaining a plurality of result values of a second hash operation by inputting an address of a second row of the plurality of rows of the memory cells into the plurality of hash control logics, and determining the second row as a candidate row for a target refresh operation based on count values of counters of the plurality of counters that are respectively indicated by the plurality of result values of the second hash operation, in a candidate selection period after the counting period;
• and
• performing the target refresh operation for rows adjacent to at least one target row of the candidate rows determined in the candidate selection period.