3d high density compact metal first approach for hybrid transistor designs without using epitaxial growth

A method comprising:

• forming a first transistor structure comprising:
• a patterned first conductive source/drain structure;
• a gate patterned conductive structure separated from the patterned first conductive source/drain structure by at least one dielectric layer;
• and
• a patterned second conductive source/drain structure separated from the gate patterned conductive structure by at least one dielectric layer;
• forming a second transistor structure comprising:
• a patterned third conductive source/drain structure;
• a second gate patterned conductive structure separated from the patterned third conductive source/drain structure by at least one dielectric layer;
• and
• a patterned fourth conductive source/drain structure separated from the second gate patterned conductive structure by at least one dielectric layer;
• forming a transistor body opening extending through the first and second transistor structures;
• forming a gate dielectric in the transistor body opening;
• and
• forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.

A method comprising:

• forming a first source/drain contact in a first dielectric layer;
• forming a gate contact in a second dielectric layer;
• forming a second source/drain contact in a third dielectric layer;
• forming a channel opening extending from at least the first source/drain contact to the second source/drain contact;
• forming a gate dielectric in the channel opening;
• and
• forming a first material in the channel opening extending from the first source/drain contact to the second source/drain contact.

A method comprising:

• forming contacts of at least two patterned transistor structures, wherein first contacts of a first patterned transistor structure and second contacts of a second patterned transistor structure are axially-aligned;
• forming a channel opening extending through the at least two patterned transistor structures;
• forming a gate dielectric associated with a contact of the first contacts;
• forming a gate dielectric associated with a contact of the second contacts;
• forming a first material in the channel opening aligned with the first contacts;
• and
• forming a second material in the channel opening aligned with the second contacts.