Apparatus, memory device, and method for multi-phase clock training

A memory controller, comprising:

• a plurality of signal pins;
• and
• a training circuit configured to transmit a clock through a first signal pin, among the plurality of signal pins, receive a three-dimensional duty offset code (3-D DOC) related to the clock through a second signal pin, and connected to a first signal line connected to the first signal pin and a second signal line connected to the second signal pin, wherein:
• the training circuit adjusts a timing of the clock based on the 3-D DOC and outputs the adjusted timing to the first signal pin, and
• the 3-D DOC is obtained by simultaneously phase-sweeping three internal clock signals in a multi-phase clock derived from the clock in a duty adjustment step by a clock training operation performed in a memory device connected to the first and second signal pins, and is configured to correct a duty error of the multi-phase clock.