Embedded source or drain region of transistor with downward tapered region under facet region

A method of manufacturing a semiconductor structure, comprising:

• providing a substrate, the substrate comprising a fin structure;
• forming an isolation structure on the substrate and surrounding the fin structure, wherein the isolation structure includes a first surface;
• forming a pair of spacers over the isolation structure;
• and
• growing a stressor material with a lattice constant different over the substrate, wherein the stressor material grows between the pair of spacers, and the growth of the stressor material comprises:
• providing a first stress on the stressor material by the pair of spacers at a first elevation abutting a bottom of the pair of spacers;
• and
• providing a second stress on the stressor material by the pair of spacers at a second elevation abutting a top of the pair of spacers, wherein the first stress is substantially greater than the second stress.

A semiconductor structure, comprising:

• a substrate, including a fin structure;
• a dielectric structure, disposed over the substrate and surrounding the fin structure, wherein a top of the fin structure is below a top surface of the dielectric structure;
• and
• a first epitaxial structure, disposed over the first fin structure, and comprises a first lower portion embedded in the dielectric structure, wherein the first lower portion includes an first lower part and a first upper part disposed over the first lower part, a first width of the first upper part is different from a second width of the first lower part.