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US 2023/0146982 A1Published application
Floating point to fixed point conversion using exponent offset
AssigneeImagination Technologies Limited
InventorKenneth Rovers
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AssigneeImagination Technologies Limited
InventorKenneth Rovers
Estimating the term…
A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes an offset unit configured to offset the exponent of the floating point number by an offset value equal to (iw−1−sy) to generate a shift value sv of sw bits given by sv=(B−E)+(iw−1−sy), the offset value being equal to a maximum amount by which the significand can be left-shifted before overflow occurs in the fixed point format; a right-shifter operable to receive a significand input comprising a formatted set of bits derived from the significand, the shifter being configured to right-shift the input by a number of bits equal to the value represented by k least significant bits of the shift value to generate an output result, where bitwidth[min(2ew-1−1, iw−1−sy)+min(2ew-1−2, fw)]≤k≤sw, where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number.
A method of converting a number in floating point format comprising an exponent E of ew bits, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the method comprising:
A method of converting a number in floating point format comprising an exponent E of ew bits, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits, the method comprising:
A non-transitory computer readable storage medium having stored thereon a computer readable dataset description of a binary logic circuit for converting a number in floating point format comprising an exponent E of ew bits, an exponent bias B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the binary logic circuit, the binary logic circuit comprising:
Dependencies are inferred from the claim text.