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US 2023/0146952 A1Published application
Transistor with faceted, raised source/drain region
AssigneeGlobalFoundries U.S. Inc.
InventorsGeorge R. MULFINGER, Matthew W. STOKER, Ryan W. SPORER, Man GU
Life of this patent
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Abstract
The present disclosure relates to semiconductor structures and, more particularly, to transistors with faceted raised source/drain regions and methods of manufacture. The structure includes: a substrate; a gate structure on the substrate; and faceted, raised source/drain regions adjacent to the gate structure and including at least two different semiconductor materials.
Claims20
A structure comprising:
- a substrate;
- a gate structure on the substrate;
- and
- faceted, raised source/drain regions adjacent to the gate structure and comprising at least two different semiconductor materials.
1 more element
A structure comprising:
- a gate structure comprising a silicided region;
- and
- a faceted, raised source/drain regions adjacent to the gate structure, the faceted, raised source/drain regions comprising a stack of epitaxial semiconductor materials and a silicided region partially into the faceted raised source/drain regions.
A method comprising:
- forming a gate structure on a substrate;
- and
- forming faceted, raised source/drain regions adjacent to the gate structure and comprising at least two different semiconductor materials.
Dependencies are inferred from the claim text.