Error correction circuit, memory system, and error correction method

A memory system comprising:

• a memory module comprising a plurality of memory devices configured to store a codeword including a main data set and a parity data set corresponding to the main data set;
• and
• a memory controller configured to:
• generate a syndrome corresponding to the codeword received from the memory module, using a parity check matrix having a value which depends on a location of an error which is a correction target,
• detect an error pattern based on the syndrome,
• generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and
• correct an error included in the codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes, during a read operation.

An error correction method comprising:

• generating a syndrome corresponding to a codeword using a parity check matrix;
• detecting an error pattern based on the syndrome;
• generating a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices which are included in the parity check matrix and correspond to N memory devices, wherein N is a natural number greater than or equal to 2;
• comparing the syndrome with the plurality of estimation syndromes;
• selecting a target memory device from among the N memory devices based on a result of the comparison;
• and
• correcting, based on the error pattern, a portion of the codeword which is output by the target memory device.