Screening of memory circuits
AssigneeTexas Instruments Incorporated
InventorsFrancisco Adolfo CANO, Devanathan VARADARAJAN, Anthony Martin HILL
Life of this patent
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Abstract
Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.
Claims14
A built-in self test (BIST) system for screening a memory array, the BIST system comprising:
- a processor configured to execute instructions, including a read instruction directed to a memory cell of the memory array, wherein the memory cell has a nominal wordline voltage and the read instruction specifies a modulated wordline voltage that is different from the nominal wordline voltage;
- an address/data generator configured to be controlled by the processor to generate, based on the instructions, a set of addresses and a set of test data that includes an expected value for the memory cell;
- margin control circuitry configured to be controlled by the processor to provide the modulated wordline voltage to a wordline of the memory cell based on the read instruction;
- a write/read control generator configured to be controlled by the processor to read the memory cell to obtain a cell value using the modulated wordline voltage;
- and
- a comparator configured to compare the cell value to the expected value.
A built-in self test (BIST) system for screening a memory cell including a first bitline, a second bitline and a wordline, the BIST system comprising:
- margin control circuitry configured to provide a modulated bitline voltage to at least one of the first bitline and the second bitline, wherein the modulated bitline voltage is different from a nominal bitline voltage of the memory cell;
- a write/read control generator configured to write a write value to the memory cell using the modulated bitline voltage, and read the memory cell to obtain a read value;
- a comparator configured to compare the read value to the write value;
- and
- a control engine coupled to, and configured to control, each of the margin control circuity, the write/read control generator, and the comparator.
A non-transitory medium storing a test program that, when executed by a processor causes a system to screen memory cells in a memory array, the test program comprising:
- read and write instructions, each read instruction including an address from which data is to be read and a wordline modulation value specifying a wordline modulation voltage to be applied to a wordline of a target memory cell during a read operation, the wordline modulation voltage being different than a nominal wordline voltage of the memory cell, and each write instruction including an indication of data to be written, an address to which data is to be written, and a bitline modulation voltage to be applied to a bitline of a target memory cell during a write operation, the bitline modulation voltage being different than a nominal bitline voltage of the memory cell;
- instructions to generate a sequence of addresses to be read from, or written to, based on the addresses in the read and write instructions and to generate test data to be written based on the write instructions;
- instructions to generate signals that cause the memory array to carry out read and write instructions, as specified by the test program, including use of the modulated wordline voltage and use of the modulated bitline voltages;
- and
- comparing, for each read instruction executed, the read data responsive to that read instruction with an expected result.
Dependencies are inferred from the claim text.