Semi-Floating Gate Memory Device and Method for Fabricating the Same

A semi-floating gate memory device, a semi-floating gate well region of a second doping type being formed on a silicon substrate of a first doping type, the first doping type being P-type and the second doping type being N-type, or the first doping type being N-type and the second doping type being P-type, wherein a U-shaped groove connected to the silicon substrate is formed in the semi-floating gate well region;

• a floating gate polysilicon layer of the first doping type is filled into the U-shaped groove and above the semi-floating gate well region covering a periphery of the U-shaped groove;
• the floating gate polysilicon layer filled into the U-shaped groove is isolated from the semi-floating gate well region by a floating gate dielectric layer;
• the floating gate polysilicon layer above the semi-floating gate well region covering the periphery of the U-shaped groove is isolated from an upper surface of the semi-floating gate well region by the floating gate dielectric layer, and is in connective contact with the semi-floating gate well region through an opening in the floating gate dielectric layer covering the upper surface of the semi-floating gate well region on a left side of the U-shaped groove;
• a control gate oxide layer covers an upper surface of the floating gate polysilicon layer;
• a control gate polysilicon layer covers an upper surface of the control gate oxide layer;
• a metal gate is located on a left part of the control gate polysilicon layer and downwards extends from a left side of the control gate polysilicon layer to an upper part of the semi-floating gate well region, and the metal gate is isolated from the control gate polysilicon layer and the semi-floating gate well region by a high-K dielectric layer;
• spacer is formed on the left side of the downwards extending part of the metal gate, the right side of the part of the metal gate above the control gate polysilicon layer, the right side of the control gate polysilicon layer, and the right side of the floating gate polysilicon layer;
• a source region and a drain region are respectively formed through silicon epitaxial growth on the semi-floating gate well region outside the left spacer of the metal gate and the semi-floating gate well region outside the right spacer of the control gate polysilicon layer;
• and
• a control gate epitaxial silicon layer is formed through silicon epitaxial growth on the control gate polysilicon layer.