Error pin training with graphics ddr memory
AssigneeAdvanced Micro Devices, Inc.
InventorsAaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
Life of this patent
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Abstract
A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.
Claims20
A method for training a receiver, comprising:
- commanding a volatile memory over a data bus to place a selected pulse-amplitude modulation (PAM) driver operating with at least three PAM levels in a mode with a designated steady output level;
- and
- at a receiver circuit coupled to the selected PAM driver, sweeping a respective reference voltage associated with the designated steady output level through a range of voltages and comparing the respective reference voltage to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.
The method of claim 3, further comprising:
- commanding the volatile memory over a data bus to place the selected PAM driver in a mode with a second designated steady output level;
- and
- at a receiver circuit coupled to the selected PAM driver, sweeping a second respective reference voltage associated with the second designated steady output level through a range of voltages and comparing the second respective reference voltage to a voltage received from the PAM driver to determine a second respective voltage level received from the PAM driver.
A physical layer (PHY) circuit for coupling to a volatile memory over a data bus, comprising:
- a pulse-amplitude modulation (PAM) receiver operating with at least three PAM levels and comprising:
- a decoder circuit;
- at least two sub-receiver circuits each including an output coupled to the decoder circuit, a first input coupled to a data bus terminal, and a second input coupled to a respective reference voltage circuit;
- and
- a receiver control circuit operable to command the volatile memory over the data bus to place a selected PAM driver in a mode with a designated steady output level;
- and
- sweep a reference voltage of a respective one of the reference voltage circuits through a range of voltages and compare the reference voltage to a voltage received from the selected PAM driver to determine a respective voltage level received from the selected PAM driver.
A memory system, comprising:
- a volatile memory;
- a data bus coupled to the volatile memory;
- and
- a memory controller comprising a physical layer (PHY) circuit coupled to the data bus and including:
- a pulse-amplitude modulation (PAM) receiver operating with at least three PAM levels and including at least two sub-receiver circuits each including a first input coupled to a data bus terminal and a second input coupled to a respective reference voltage circuit;
- and
- a receiver control circuit operable to command the volatile memory over the data bus to place a selected PAM driver in a mode with a designated steady output level;
- and sweep a reference voltage of a respective one of the reference voltage circuits through a range of voltages and compare the reference voltage to a voltage received from the selected PAM driver to determine a respective voltage level received from the selected PAM driver.
Dependencies are inferred from the claim text.