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US 2023/0146689 A1Published application
Deep neural network
AssigneeBrown University
InventorsSherief REDA, Hokchhay TANN, Soheil HASHEMI, R. Iris BAHAR
Life of this patent
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Abstract
A hardware neural network system includes an input buffer for input neurons (Nbin), an output buffer for output neurons (Nbout), and a third buffer for synaptic weights (SB) connected to a Neural Functional Unit (NFU) and a control logic (CP) for performing synapses and neurons computations. The NFU pipelines a computation into stages, the stages including weight blocks (WB), an adder tree, and a non-linearity function.
Claims8
A hardware neural network system comprising:
- an input buffer for input neurons (Nbin);
- an output buffer for output neurons (Nbout);
- and
- a third buffer for synaptic weights (SB) connected to a Neural Functional Unit (NFU) and a control logic (CP) for performing synapses and neurons computations.
1 more element
A method comprising:
- mapping floating-point based Deep Neural Networks (DNNs) to 8-bit dynamic fixed-point networks with integer power-of-two weights with no change in network architecture, the 8-bit dynamic fixed-point DNNs enabling different radix points between layers.
A hardware accelerator comprising:
- memory subsystems used to store intermediate values and outputs and buffer inputs and weights, the memory systems comprising an SRAM buffer array, a DMA, and control logic responsible for ensuring that data is loaded into buffers and made available to a neural functional unit (NFU) at an appropriate clock cycle without additional latency.
Dependencies are inferred from the claim text.