Memory device

A memory device comprising:

• a memory cell array connected to a sensing bit line and a sensing complementary bit line;
• a local bit line sense amplifier configured to output a first signal output on the sensing bit line to a first bit line and output a complementary signal output on the sensing complementary bit line to a complementary bit line;
• a first charge transfer transistor connected between the sensing bit line and the first bit line and the first charge transfer transistor configured to be turned on or off based on a charge transfer signal of a first node;
• and
• a second charge transfer transistor connected between the sensing complementary bit line and the complementary bit line and the second charge transfer transistor configured to be turned on or off based on the charge transfer signal,
• wherein the local bit line sense amplifier includes a first equalizing transistor which is connected between a second node and the sensing complementary bit line and gated by a signal of the second node;
• and
• the local bit line sense amplifier is configured such that a pre-charging voltage is supplied to the second node during an offset removal operation and such that the first node is connected to the second node during the offset removal operation.

A memory device comprising:

• a memory cell array in a memory bank region of a buffer die and including a plurality of memory cells;
• a plurality of local bit line sense amplifiers between the memory bank regions and the plurality of local bit line sense amplifiers being connected between the memory cell and a first bit line or between the memory cell and a complementary bit line;
• a global connection controller in a conjunction region of the buffer die and the global connection controller configured to control an operation of the local bit line sense amplifier;
• and
• a charge transfer transistor configured to connect a sensing bit line of the local bit line sense amplifier to the first bit line and a sensing complementary bit line of the local bit line sense amplifier to the complementary bit line, in response to a charge transfer signal supplied via a first node of the global connection controller being applied to a gate of the charge transfer transistor, and
• wherein the global connection controller connects the first node and a second node while supplying a pre-charging voltage to the second node, a gate of a first equalizing transistor of the local bit line sense amplifier being connected to the second node during an offset removal operation.