Systems and methods for staggering read operation of sub-blocks
AssigneeSanDisk Technologies LLC
InventorsYu-Chung Lien, Deepanshu Dutta, Tai-Yuan Tseng
Life of this patent
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Abstract
A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.
Claims20
A method for optimizing an operation of a memory device, the method comprising the steps of:
- accessing, by a first row decoder, a first sub-block of a first memory block at a first time;
- and
- accessing, by a second row decoder, a second sub-block of a second memory block at a second time that is different from the first time.
A memory system, comprising:
- a memory device;
- and
- a controller operatively coupled to the memory device, the controller being configured to:
- access, by a first row decoder, a first sub-block of a first memory block at a first time;
- and
- access, by a second row decoder, a second sub-block of a second memory block at a second different from the first time.
A non-transitory computer readable storage medium configured to store instructions that, when executed by a processor includes a controller of a memory system, cause the memory system to carry out steps to:
- access, by a first row decoder, a first sub-block of a first memory block at a first time;
- and
- access, by a second row decoder, a second sub-block of a second memory block at a second different from the first time.
Dependencies are inferred from the claim text.