Memory with dqs pulse control circuitry, and associated systems, devices, and methods

A memory system, comprising:

• a memory controller;
• and
• a memory device operably connected to the memory controller, wherein the memory device includes:
• an external terminal configured to receive an external timing signal from the memory controller, the external timing signal including a first pulse having a first pulse width;
• and
• circuitry operably coupled to the external terminal, wherein the circuitry is configured to:
• generate a second pulse based at least in part on the first pulse, wherein the second pulse has a second pulse width greater than the first pulse width, and
• output an internal timing signal including the second pulse.

A circuit, comprising:

• a set/reset (SR) latch;
• and
• a delay element having (a) an input operably connected to an output of the SR latch and (b) an output operably connected to a second input of the SR latch,
• wherein:
• the circuit is configured to receive an input corresponding to an external timing signal, and
• the circuit is further configured to output an internal timing signal based at least in part on the external timing signal.