Method and device with neural network model
AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsSungjoo YOO, Seungyeop KANG
Life of this patent
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Abstract
A device includes: a comparator; an exclusive-NOR (XNOR) gate; an accumulator; and a multiplication and accumulation (MAC) operator, wherein a basic block of a neural network comprises a first batch normalization layer, a quantization layer, a convolution layer, an active layer, and a second batch normalization layer, and wherein the basic block is driven by the device by a combination of a first batch normalization operation, a sign function operation, a bitwise convolution operation, an activation function operation, a second batch normalization operation, and a residual connection operation.
Claims19
A device, the device comprising:
- a comparator;
- an exclusive-NOR (XNOR) gate;
- an accumulator;
- and
- a multiplication and accumulation (MAC) operator,
- wherein a basic block of a neural network comprises a first batch normalization layer, a quantization layer, a convolution layer, an active layer, and a second batch normalization layer, and
- wherein the basic block is driven by the device by a combination of a first batch normalization operation, a sign function operation, a bitwise convolution operation, an activation function operation, a second batch normalization operation, and a residual connection operation.
A processor-implemented method, the method comprising:
- quantizing input data by comparing a result of performing a sign function operation on transformed input data with a predetermined value using a comparator;
- performing a bitwise convolution operation using an exclusive-NOR (XNOR) gate and an accumulator;
- and
- performing an activation function operation and a residual connection operation using a multiplication and accumulation (MAC) operator.
An electronic device, the electronic device comprising:
- a host processor configured to control an operation of components comprised in the electronic device;
- and
- a hardware accelerator configured to process input data by executing a neural network based on a command of the host processor,
- wherein the hardware accelerator comprises:
- a comparator;
- an exclusive-NOR (XNOR) gate;
- an accumulator;
- and
- a multiplication and accumulation (MAC) operator.
A device, the device comprising:
- a hardware accelerator configured to, for a first neural network operation:
- quantize input data by comparing a predetermined value with a result of performing a sign function operation on transformed input data, the transformed input data being determined using a first batch normalization operation;
- perform a bitwise convolution operation on the quantized input data;
- determine output data by applying an activation function to a result of the bitwise convolution operation;
- multiply a first portion of a second batch normalization operation by the output data;
- and
- perform an operation of adding a result of the multiplying and input data.
Dependencies are inferred from the claim text.