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US 2023/0146377 A1Published application
Memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJung Min YOU, Seong-Jin CHO
Life of this patent
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Abstract
According to an embodiment, a memory device includes a memory cell array including a plurality of memory cells; and a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.
Claims20
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a control logic which includes a mode register, performs a refresh operation in response to a refresh command, generates an internal mode register write command in response to the refresh command in a first mode, and does not generate the internal mode register write command in response to the refresh command in a second mode.
A memory system, comprising:
- a memory controller configured to generate a refresh command;
- and
- a memory device which includes a memory cell array and a control logic, the memory cell array including a plurality of memory cells, the control logic including a mode register and configured to perform a refresh operation in response to the refresh command,
- wherein the memory device stores a bank address and a row address, on which the refresh operation is performed, in the mode register, or outputs the bank address and the row address to the memory controller.
1 more element
A memory device, comprising:
- a memory cell array including a plurality of memory cells;
- and
- a control logic including a mode register,
- wherein:
- the control logic outputs a first bank address and a first row address in response to a mode register read command in at least a portion of a period in which a first refresh operation is performed by receiving a first refresh command, and outputs a second bank address and a second row address in response to the mode register read command in at least a portion of a period in which a second refresh operation is performed by receiving a second refresh command;
- the second bank address is different from the first bank address;
- and
- the second row address is different from the first row address.
5 more elements
Dependencies are inferred from the claim text.