Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsYasuo AITA, Daisuke KAWAKAMI, Toshiyuki HIRAKI
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a processing unit that issue a memory access request with a virtual address, a first and a second memory management unit and a test result storage unit. The first and the second memory management unit are hierarchically provided, and each include address translation unit translating the virtual memory of the memory access request into a physical address and self-test unit testing for the address translation unit. The test result storage unit stores a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.
Claims16
A semiconductor device, comprising:
- a processing unit configured to issue a memory access request with a virtual address;
- a first memory management unit coupled to the processing unit, and
- a second memory management unit coupled to the first memory management unit;
- wherein the first memory management unit includes:
- a first address translation unit translating the virtual address of the memory access request into a physical address, and
- a first self-test unit testing for the first address translation unit;
- wherein the second memory management unit includes:
- a second address translation unit translating the virtual address of the memory access request into a physical address if the virtual address of the memory access request is not translated by the first address translation unit, and
- a second self-test unit testing for the second address translation unit;
- a result storage unit storing a first self-test result that indicates a result of the first self-test unit and a second self-test result that indicates a result of the second self-test unit.
A semiconductor device comprising:
- a memory access request unit configured to issue a memory access request having a virtual address;
- a first memory management unit having a first address translation unit and a first self-test unit, the first address translation unit having a first translation lookaside buffer storing a first part of a page table of a memory, the first self-test unit being configured to testing the first address translation unit;
- a second memory management unit having a second address translation unit and a second self-test unit, the second address translation unit having a second translation lookaside buffer that includes a second part of the page table of the memory and is accessed if the first lookaside buffer does not include a page table entry corresponding to the virtual address of the memory access request, the second self-test unit being configured to test for the second address translation unit,
- a test result storage unit storing a first test result of the first self-test unit and a second test result of the second self-test unit.
A semiconductor device comprising:
- a central processing unit (CPU);
- a dedicated processing unit configured to issue a memory access request with a virtual address;
- a first memory management unit coupled to the processing unit and translating the virtual address of the memory access request into a physical address;
- a second memory management unit coupled to the first memory management unit and translating the virtual address of the memory access request into the physical address if the first memory management unit does not translate the virtual address of the memory access request;
- a first self-test unit configured to detect an address translation function error of the first memory management unit, and,
- a second self-test unit configured to detect an address translation function error of the second memory management unit,
- wherein the CPU instructs a reset operation for at least one of the first and the second memory management unit based on error detection results of the first and the second self-test unit.
Dependencies are inferred from the claim text.