US 2023/0146151 A1Published application

Semiconductor devices

AssigneeSamsung Electronics Co., Ltd.

InventorJongmin LEE

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Abstract

A semiconductor device includes gate structures, bit line structures, contact plug structures, first capacitors, and second capacitors. The gate structures are formed in a substrate including a cell region and a peripheral circuit region, and each of the gate structures extends in a first direction. The bit line structures are formed on the cell region of the substrate, and each of the bit line structures extends in a second direction. The contact plug structures are disposed in the second direction between the bit line structures on the substrate. The first capacitors are formed on the contact plug structures, respectively. The conductive pad is formed on the peripheral circuit region of the substrate, and is electrically insulated from the substrate. The second capacitors are formed on the conductive pad, and are disposed in the first and second directions.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate including a cell region and a peripheral circuit region;
gate structures on the cell region of the substrate, each of the gate structures extending in a first direction substantially parallel to an upper surface of the substrate;
bit line structures on the cell region of the substrate, each of the bit line structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction;
contact plug structures disposed in the second direction between the bit line structures on the substrate;
first capacitors on the contact plug structures, respectively;
a conductive pad on the peripheral circuit region of the substrate, the conductive pad being electrically insulated from the substrate;
and
second capacitors on the conductive pad, the second capacitors being arranged in the first and second directions,
wherein:
each of the first capacitors includes:
a first lower electrode having a first cup shape;
a first dielectric pattern on a surface of the first lower electrode, the first dielectric pattern filling an inner space of the first cup shape of the first lower electrode;
and
a first upper electrode on a surface of the first dielectric pattern, and
each of the second capacitors includes:
a second lower electrode having a second cup shape;
a second dielectric pattern on a surface of the second lower electrode;
and
a second upper electrode on a surface of the second dielectric pattern,
wherein the second dielectric pattern and the second upper electrode fill an inner space of the second cup shape of the second lower electrode.

17 more elements

A semiconductor device comprising:

a substrate including a cell region and a peripheral circuit region;
gate structures on the cell region of the substrate, each of the gate structures extending in a first direction substantially parallel to an upper surface of the substrate in the cell region;
bit line structures on the cell region of the substrate, each of the bit line structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction;
contact plug structures disposed in the second direction between the bit line structures on the substrate;
first capacitors on the contact plug structures, respectively;
a conductive pad on the peripheral circuit region of the substrate, the conductive pad being electrically insulated from the substrate;
and
second capacitors on the conductive pad, the second capacitors being arranged in the first and second directions,
wherein:
each of the first capacitors includes:
a first lower electrode having a first cup shape;
a first dielectric pattern on a surface of the first lower electrode;
a first upper electrode on a surface of the first dielectric pattern;
and
a third upper electrode on a surface of the first upper electrode, and
each of the second capacitors includes:
a second lower electrode having a second cup shape;
a second dielectric pattern on a surface of the second lower electrode;
a second upper electrode on a surface of the second dielectric pattern;
and
a fourth upper electrode on a surface of the second upper electrode,
wherein the second dielectric pattern, the second upper electrode and the fourth upper electrode fill an inner space of the second cup shape of the second lower electrode.

19 more elements

A semiconductor device comprising:

a substrate including a cell region and a peripheral circuit region;
gate structures on the cell region of the substrate, each of the gate structures extending in a first direction substantially parallel to an upper surface of the substrate;
bit line structures on the cell region of the substrate, each of the bit line structures extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction;
contact plug structures disposed in the second direction between the bit line structures on the substrate;
first capacitors on the contact plug structures, respectively;
a conductive pad on the peripheral circuit region of the substrate, the conductive pad being electrically insulated from the substrate;
and
second capacitors on the conductive pad, the second capacitors being arranged in the first and second directions,
wherein:
each of the first capacitors includes:
a first lower electrode having a pillar shape;
a first dielectric pattern on a surface of the first lower electrode;
a first upper electrode on a surface of the first dielectric pattern;
and
a third upper electrode on a surface of the first upper electrode,
each of the second capacitors includes:
a second lower electrode having a cup shape;
a second dielectric pattern on a surface of the second lower electrode;
a second upper electrode on a surface of the second dielectric pattern;
and
a fourth upper electrode on a surface of the second upper electrode, and
the second dielectric pattern, the second upper electrode and the fourth upper electrode fill an inner space of the cup shape of the second lower electrode.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/944,407Filed 14 Sep 2022
Priority: KR 10-2021-015415610 Nov 2021
Published: 11 May 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10B 12/50
Dynamic random access memory [DRAM] devices: peripheral circuit region structures
H10D 1/716
Having non-planar surfaces, e.g. formed by texturisation: having vertical extensions
H10B 12/0335
The capacitor extending over the transistor: making a connection between the transistor and the capacitor, e.g. plug
H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells